Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Renesas 70V659S12DR

Name: 70V659S12DR
Brand: Renesas
SKU: 70V659S12DR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 70V659S12DR

Manufacturer:: Renesas

Category:: Memory

Package:: 208-BFQFP

Datasheet:: 70V659S12DR.pdf

Description:: IC SRAM 4.5MBIT PARALLEL 208PQFP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,156

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

70V659S12DR from IDT is a high-speed 128K × 36 asynchronous dual-port static RAM with true independent left/right ports, 12 ns max access time (commercial/industrial), LVTTL-compatible 3.3 V core supply, and selectable 3.3 V/2.5 V I/O voltage per port via OPT pins - used in real-time inter-processor communication, FPGA co-processor buffering, and telecom packet memory subsystems.

For engineers reviewing the 70V659S12DR datasheet, 70V659S12DR pinout, 70V659S12DR application, or 70V659S12DR equivalent, this page delivers verified pin functions, bus arbitration timing, JTAG-compliant test support, byte-selectable 9-bit write control, and industrial-grade (-40°C to +85°C) operation for deterministic dual-access memory systems.

Technical Context

The 70V659S12DR implements fully asynchronous dual-port architecture with separate address, control, and bidirectional I/O buses for left (L) and right (R) ports - enabling simultaneous read/write to the same memory location without external arbitration logic. On-chip semaphore logic supports eight shared flags accessed via A0–A2 and I/O0–I/O35.

Port arbitration uses dedicated BUSY/INT/SEM signals and Master/Slave (M/S) configuration: when M/S = VIH, BUSY is an output flag indicating contention; when M/S = VIL, BUSY is an input that gates writes on the slave port. JTAG (IEEE 1149.1) is supported via TDI/TDO/TCK/TMS/TRST pins for boundary-scan testing.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128K × 36 bits (4.608 Mbit); supports 72-bit+ expansion via MASTER/SLAVE cascading
Access Time	12 ns max (70V659S12DR grade); guarantees full-speed operation in ≤12 ns cycle systems
Supply Voltages	VDD = 3.3 V ±150 mV (core); VDDQL/VDDQR = 3.3 V ±150 mV or 2.5 V ±100 mV (I/O, selectable per port)
Operating Temperature	-40°C to +85°C (industrial grade); validated for continuous operation across full range
I/O Interface	LVTTL-compatible; 36 bidirectional data lines per port (I/O0L–I/O35L / I/O0R–I/O35R)
Arbitration Logic	On-chip hardware semaphore, BUSY flag, and interrupt signaling - eliminates need for external logic
JTAG Support	IEEE 1149.1 compliant with TDI/TDO/TCK/TMS/TRST; enables production test and debug visibility

Pinout & Package

70V659S12DR is packaged in a 208-pin Plastic Quad Flatpack (PQFP), 28 mm × 28 mm × 3.5 mm body, with 0.5 mm lead pitch. All VDD pins require 3.3 V connection; VDDQL/VDDQR must match OPTL/OPTR selection (3.3 V if OPT = VDD, 2.5 V if OPT = VSS); all VSS pins connect to ground.

Pin/Terminal	Circuit Role	Design Meaning
CE0L, CE1L / CE0R, CE1R	Chip Enable (dual per port)	Independent port enable; CE0X = VIL & CE1X = VIH selects port X; enables depth expansion without glue logic
R/WL / R/WR	Read/Write Control	Active-low write enable; determines direction of data transfer on respective port
OEL / OER	Output Enable	Controls tri-state of I/O drivers; required for valid read data output
BE0L–BE3L / BE0R–BE3R	Byte Enable (4 × 9-bit)	Selects individual 9-bit bytes (I/O0–8, 9–17, 18–26, 27–35) for partial writes - critical for mixed-width bus interfacing
A0L–A16L / A0R–A16R	Address Inputs	17-bit address per port; A16 is no-connect for 64K/32K configurations (per datasheet note)
I/O0L–I/O35L / I/O0R–I/O35R	Bidirectional Data Bus	36-bit parallel data path per port; supports simultaneous independent access
SEML / SEMR	Semaphore Enable	Activates semaphore register access (A0–A2 address 8 flags); CE = VIH & SEM = VIL required
BUSYL / BUSYR	Busy Flag	Output when M/S = VIH (Master); input when M/S = VIL (Slave); blocks conflicting writes during contention
INTL / INTR	Interrupt Flag	Active-high totem-pole output; signals semaphore or arbitration event to host processor
M/S	Master/Slave Select	Configures device role: VIH = Master (BUSY output), VIL = Slave (BUSY input); enables multi-device synchronization
OPTL / OPTR	I/O Voltage Select	Set to VDD (3.3 V) or VSS (0 V) to configure corresponding port's I/O voltage level and VDDQX supply
TDI, TDO, TCK, TMS, TRST	JTAG Test Interface	Enables IEEE 1149.1 boundary-scan; supports production test, debug, and system-level verification

Key Features

Feature	Design Value
True Dual-Port Architecture	Simultaneous independent read/write to identical memory locations - eliminates software locks and improves throughput in real-time IPC
Per-Port I/O Voltage Selection	OPTL/OPTR pins allow left/right ports to operate at 3.3 V or 2.5 V independently - simplifies interfacing with mixed-voltage SoCs/FPGAs
Hardware Semaphore Logic	Eight shared flags accessible via A0–A2 and I/O0–I/O35 - enables atomic resource sharing between processors without CPU intervention
Dual Chip Enables per Port	CE0X/CE1X pair allows seamless depth expansion (e.g., 2× devices for 256K×36) - no external decode logic required
Industrial Temperature Range	Validated operation from -40°C to +85°C - suitable for base station, industrial control, and avionics applications
JTAG Boundary-Scan Support	Fully compliant with IEEE 1149.1 - enables automated PCB test, fault isolation, and in-system debugging

Applications

Telecom Packet Buffering	FPGA-CPU Co-Processor Interface
Use Scenario: Storing variable-length Ethernet/SONET frames in line cards where ingress and egress paths require concurrent access. IC Role / Device Role / Timing Role: Dual-port SRAM acts as zero-latency shared buffer between MAC and traffic manager; left port handles ingress, right port handles egress. Use Value: Eliminates FIFO bottlenecks and enables deterministic frame forwarding with 12 ns access - critical for sub-10 µs latency SLAs.	Use Scenario: Real-time data exchange between Xilinx Zynq FPGA programmable logic and ARM Cortex-A9 processing subsystem. IC Role / Device Role / Timing Role: 70V659S12DR serves as low-latency mailbox memory; FPGA writes status/control words, CPU reads them asynchronously. Use Value: Hardware semaphore ensures atomic flag updates; per-port 2.5 V/3.3 V I/O matching avoids level shifters in heterogeneous interface design.
Multi-Core DSP Inter-Processor Communication	Radar Signal Processing Pipeline
Use Scenario: Synchronizing radar pulse-Doppler processing tasks across two TI C66x DSP cores sharing common coefficient tables and intermediate results. IC Role / Device Role / Timing Role: Acts as shared memory with BUSY-flag arbitration; one core writes processed samples while the other reads for FFT staging. Use Value: On-chip arbitration prevents bus collisions; 12 ns access sustains >80 MB/s sustained bandwidth per port - exceeds C66x EMIF limits.	Use Scenario: Storing phase-aligned ADC samples in airborne radar front-end before digital beamforming, requiring simultaneous capture and analysis. IC Role / Device Role / Timing Role: Left port captures ADC stream at 100 MSPS; right port feeds beamformer engine - both accessing overlapping memory regions. Use Value: True dual-port cell structure enables lock-free sample handoff; industrial temp rating ensures reliability in sealed radar enclosures.

Telecom Packet Buffering

FPGA-CPU Co-Processor Interface

Use Scenario: Storing variable-length Ethernet/SONET frames in line cards where ingress and egress paths require concurrent access.

IC Role / Device Role / Timing Role: Dual-port SRAM acts as zero-latency shared buffer between MAC and traffic manager; left port handles ingress, right port handles egress.

Use Value: Eliminates FIFO bottlenecks and enables deterministic frame forwarding with 12 ns access - critical for sub-10 µs latency SLAs.

Use Scenario: Real-time data exchange between Xilinx Zynq FPGA programmable logic and ARM Cortex-A9 processing subsystem.

IC Role / Device Role / Timing Role: 70V659S12DR serves as low-latency mailbox memory; FPGA writes status/control words, CPU reads them asynchronously.

Use Value: Hardware semaphore ensures atomic flag updates; per-port 2.5 V/3.3 V I/O matching avoids level shifters in heterogeneous interface design.

Multi-Core DSP Inter-Processor Communication

Radar Signal Processing Pipeline

Use Scenario: Synchronizing radar pulse-Doppler processing tasks across two TI C66x DSP cores sharing common coefficient tables and intermediate results.

IC Role / Device Role / Timing Role: Acts as shared memory with BUSY-flag arbitration; one core writes processed samples while the other reads for FFT staging.

Use Value: On-chip arbitration prevents bus collisions; 12 ns access sustains >80 MB/s sustained bandwidth per port - exceeds C66x EMIF limits.

Use Scenario: Storing phase-aligned ADC samples in airborne radar front-end before digital beamforming, requiring simultaneous capture and analysis.

IC Role / Device Role / Timing Role: Left port captures ADC stream at 100 MSPS; right port feeds beamformer engine - both accessing overlapping memory regions.

Use Value: True dual-port cell structure enables lock-free sample handoff; industrial temp rating ensures reliability in sealed radar enclosures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
CY7C1362BV33-12BGXI	128K × 36, 12 ns, 3.3 V only (no 2.5 V I/O option), BGA256 package, no JTAG	Lacks per-port voltage select and IEEE 1149.1 test support; requires fixed 3.3 V I/O interface	Choose when JTAG and mixed-voltage I/O are unnecessary and BGA footprint is preferred.
AS7C3128B-12JIN	128K × 36, 12 ns, 3.3 V core/I/O, PQFP208, no semaphore or BUSY logic	No hardware arbitration - external logic needed for multi-processor sync; no semaphore registers	Choose for cost-sensitive designs where software-managed locking suffices and arbitration logic is implemented externally.

Compared with CY7C1362BV33-12BGXI and AS7C3128B-12JIN, the 70V659S12DR uniquely integrates per-port I/O voltage selection, IEEE 1149.1 JTAG, and hardware semaphore/BUSY arbitration - reducing BOM count and improving determinism in tightly coupled multi-processor systems.

Availability

70V659S12DR is available at Aetrix Electronics and suitable for telecom infrastructure, industrial control, and aerospace embedded systems requiring stable component supply, long-lifecycle support, and guaranteed industrial temperature performance.

Supply support for 70V659S12DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, RF, and sensor solutions - acquired by Renesas in 2019.

The 70V659S12DR belongs to IDT's high-speed asynchronous dual-port SRAM product line, designed specifically for deterministic inter-processor communication, real-time buffering, and hardware-accelerated synchronization in telecom, defense, and industrial systems.

FAQ

What is the maximum operating frequency supported by the 70V659S12DR?

The 70V659S12DR does not operate on a clock signal - it is an asynchronous dual-port SRAM. Its timing is defined by access and cycle times: 12 ns maximum address access time (tAA), 12 ns maximum read cycle time (tRC), and 12 ns maximum write cycle time (tWC). These parameters enable reliable operation in systems with effective data rates up to ~83 MHz for burst transfers, assuming proper setup/hold timing is met.

How does the Master/Slave (M/S) pin affect BUSY signal behavior in the 70V659S12DR?

In the 70V659S12DR, the M/S pin configures BUSY functionality: when M/S = VIH, BUSY is an active-high totem-pole output that asserts during port contention; when M/S = VIL, BUSY becomes an active-high input that must be driven externally to gate writes on the slave port. This dual-mode design enables flexible multi-device arbitration topologies without external logic.

Can the left and right ports of the 70V659S12DR operate at different I/O voltages simultaneously?

Yes. The 70V659S12DR supports independent I/O voltage selection per port via OPTL and OPTR pins. Setting OPTL = VDD (3.3 V) and OPTR = VSS (0 V) configures the left port for 3.3 V I/O levels (requiring VDDQL = 3.3 V) and the right port for 2.5 V I/O levels (requiring VDDQR = 2.5 V). This capability simplifies interfacing with heterogeneous processors or FPGAs on the same board.

What is the function of the semaphore logic in the 70V659S12DR, and how is it accessed?

The 70V659S12DR includes eight hardware semaphore flags used for atomic resource sharing between processors. They are accessed by setting CE = VIH and SEM = VIL (opposite of normal RAM access), then using A0–A2 to select the flag and I/O0 to write or all I/O lines to read. This dedicated path ensures contention-free flag updates without affecting main memory operations.

Does the 70V659S12DR support JTAG boundary-scan, and which pins are used?

Yes, the 70V659S12DR fully supports IEEE 1149.1 JTAG boundary-scan. It uses five dedicated pins: TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), and TRST (Test Reset). These enable production test, fault diagnosis, and in-system verification - confirmed in the Functional Block Diagram and Pin Names table of the official datasheet.

70V659S12DR Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 208-BFQFP

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Memory Type:: Volatile

Memory Format:: SRAM

Technology:: SRAM - Dual Port, Asynchronous

Memory Size:: 4.5Mbit

Memory Organization:: 128K x 36

Memory Interface:: Parallel

Clock Frequency:: -

Write Cycle Time - Word, Page:: 12ns

Access Time:: 12 ns

Voltage - Supply:: 3.15V ~ 3.45V

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 208-PQFP (28x28)

70V659S12DR FAQ

1.How can I place an order for 70V659S12DR through Aetrix?

Please submit a Request for Quotation (RFQ) for 70V659S12DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 70V659S12DR reliable?

The price and inventory of 70V659S12DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 70V659S12DR is usually 5 days.

3.What payment methods are accepted for 70V659S12DR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 70V659S12DR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 70V659S12DR?

70V659S12DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 70V659S12DR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 70V659S12DR?

For technical support, including 70V659S12DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 70V659S12DR requirements.

6.How does Aetrix verify that 70V659S12DR is sourced from the original manufacturer or authorized distributors?

All 70V659S12DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 70V659S12DR meets industry standards.

7.What is the process for return or replacement of 70V659S12DR?

All 70V659S12DR units undergo pre-shipment inspection (PSI). If there is an issue with 70V659S12DR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 70V659S12DR part is unused and in its original packaging.

Return procedure for 70V659S12DR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…