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Renesas 7130LA35PF
- Part No.:
- 7130LA35PF
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 64-LQFP
- Datasheet:
-
7130LA35PF.pdf
- Description:
- IC SRAM 8KBIT PARALLEL 64TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,712
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Product details
Overview
7130LA35PF from IDT is a high-speed 1K × 8 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 35 ns maximum read cycle time, 1 mA typical standby current (LA version), and battery backup data retention down to 2 V. It enables error-free 16-bit-or-wider memory expansion when paired with IDT7140 SLAVE devices in real-time industrial control systems.
For engineers reviewing the 7130LA35PF datasheet, 7130LA35PF pinout, 7130LA35PF application, or 7130LA35PF equivalent, this page delivers verified timing parameters, port arbitration behavior, BUSY/INT flag operation, and package-specific DC/AC electrical characteristics for deterministic dual-ported memory integration.
Technical Context
The 7130LA35PF implements fully asynchronous dual-port access with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves contention via BUSY output assertion and supports port-to-port interrupt signaling using INTL/INTR flags.
It features open-drain BUSY outputs requiring external pull-up resistors, TTL-compatible 5 V ±10% supply operation, and CMOS-level full-standby mode enabling 0.2 µA typical ISB3 current. Battery backup data retention at 2 V applies exclusively to LA-grade variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Organization | 1K × 8 (1024 words × 8 bits), dual independent ports |
| Max Read Cycle Time (tRC) | 35 ns - defines minimum interval between successive reads on same port |
| Standby Current (ISB3) | 0.2 µA typical - ultra-low power consumption in full CMOS standby mode |
| Data Retention Voltage | 2.0 V - maintains stored data during brown-out or backup battery operation |
| Supply Voltage | 4.5–5.5 V - single TTL-compatible rail, no auxiliary supplies required |
| Operating Temperature | –40°C to +85°C - qualified for industrial environments without derating |
| Package | 48-pin Flatpack (FP48) - hermetically sealed ceramic package for high-reliability applications |
Pinout & Package
7130LA35PF is supplied in a 48-pin ceramic flatpack (FP48) measuring approximately 0.75 in × 0.75 in × 0.11 in, with side-brazed leads and index mark at Pin 1. All VCC pins require direct connection to 5 V supply; all GND pins must be tied to system ground.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A9L | Left port address inputs | 10-bit address bus for left-side memory access (0–1023) |
| A0R–A9R | Right port address inputs | 10-bit address bus for right-side memory access (0–1023) |
| I/O0L–I/O7L | Left port bidirectional data | 8-bit data path; direction controlled by R/WL and OEL |
| I/O0R–I/O7R | Right port bidirectional data | 8-bit data path; direction controlled by R/WR and OER |
| CEL, CER | Chip enable (active low) | Port-selective enable; deassertion places port in standby (ISB2/ISB4) |
| OEL, OER | Output enable (active low) | Controls I/O drivers; high-Z when asserted while R/W = H |
| R/WL, R/WR | Read/write control | Active-high = read, active-low = write; determines I/O direction |
| BUSYL, BUSYR | Arbitration status outputs | Open-drain flags indicating port contention; require external pull-up |
| INTL, INTR | Interrupt request outputs | Active-low flags for inter-port communication; set/clear via dedicated addresses |
| VCC, GND | Power and ground | Multiple distributed pins ensure stable supply delivery and noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| On-chip arbitration logic | Resolves simultaneous access to same address without external logic; uses BUSY outputs to stall contending port |
| Port-to-port interrupt signaling | INTL/INTR flags support handshake protocols between processors or DMA engines sharing memory |
| Battery backup data retention | Maintains valid data at 2 V supply - enables seamless transition to backup power in critical systems |
| Master/Slave expandability | 7130LA35PF acts as MASTER; pairs with IDT7140 SLAVE to build 16-bit+ word-width memory without speed penalty |
| Ultra-low standby power | 0.2 µA typical ISB3 current enables years of retention on coin-cell batteries in unpowered state |
Applications
| Real-Time Industrial PLC | Dual-CPU Communication Buffer |
|---|---|
Use Scenario: Two independent microcontrollers exchange sensor data and control commands via shared memory in a programmable logic controller. IC Role / Device Role / Timing Role: 7130LA35PF serves as MASTER dual-port SRAM with hardware arbitration, eliminating software locks and ensuring deterministic latency. Use Value: 35 ns tRC and sub-1 µA standby current enable fast, low-power inter-processor messaging without bus contention errors. | Use Scenario: A host CPU writes configuration data to a field-programmable gate array (FPGA), which reads it at boot and signals completion via interrupt. IC Role / Device Role / Timing Role: 7130LA35PF provides synchronized, non-blocking memory access; INTL/INTR flags replace polling overhead. Use Value: Hardware interrupt generation reduces FPGA boot latency by >90% versus software-polling schemes. |
| Avionics Data Logger | Redundant Control System Memory |
Use Scenario: Flight data recorder captures telemetry from multiple sensors while simultaneously allowing ground maintenance interface to read logs. IC Role / Device Role / Timing Role: 7130LA35PF operates as MASTER with BUSY-controlled arbitration, preventing corruption during concurrent capture/read operations. Use Value: 2 V data retention ensures log integrity during main power loss; FP48 package meets MIL-PRF-38535 QML reliability standards. | Use Scenario: Safety-critical rail signaling system uses two independent processors monitoring each other's health via mirrored memory regions. IC Role / Device Role / Timing Role: 7130LA35PF provides bit-identical, lock-step memory access with hardware-enforced priority via tAPS timing. Use Value: Arbitration priority setup time (tAPS = 5 ns) guarantees fail-safe response within SIL-3 timing budgets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C131-35PC | 35 ns access, 5 V, 1K × 8, but no on-chip arbitration or BUSY logic; requires external glue logic for contention resolution | Lacks native port-to-port interrupt and arbitration - unsuitable for MASTER role in multi-processor systems | Select only if arbitration handled externally and footprint allows DIP-28 vs FP48 |
| IDT7140LA35PF | Same speed, package, and LA retention, but SLAVE-only: BUSY inputs (not outputs), no arbitration logic, no INT flag generation | Cannot operate standalone; must be paired with 7130LA35PF as SLAVE in 16-bit expansion | Use only as companion SLAVE in MASTER/SLAVE configurations - not a functional substitute |
Compared with CY7C131-35PC and IDT7140LA35PF, the 7130LA35PF uniquely integrates arbitration, BUSY signaling, and interrupt generation in a single MASTER device - enabling simpler, more reliable dual-processor memory sharing without discrete logic or timing-critical firmware coordination.
Availability
7130LA35PF is available at Aetrix Electronics and suitable for real-time industrial PLCs, avionics data loggers, and redundant control systems requiring stable component supply, long-term lifecycle support, and MIL-qualified packaging.
Supply support for 7130LA35PF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance timing, memory, and interface solutions for communications, computing, and industrial markets.
The IDT7130/7140 family was designed specifically for deterministic, contention-free dual-processor memory sharing in mission-critical embedded systems - emphasizing hardware arbitration, low-power retention, and military-grade reliability.
FAQ
What is the maximum operating temperature range for the 7130LA35PF?
The 7130LA35PF is rated for industrial temperature operation from –40°C to +85°C. This rating is confirmed in the "Recommended Operating Temperature and Supply Voltage" table (2689 tbl 03) and applies across all AC/DC specifications for the LA grade. It does not support extended military ranges (–55°C to +125°C) unless explicitly ordered as MIL-PRF-38535 QML-compliant variant.
Does the 7130LA35PF support true dual-port read/write without external arbitration logic?
Yes, the 7130LA35PF contains on-chip arbitration logic that automatically manages contention when both ports access the same memory location. BUSYL and BUSYR outputs signal contention, and the device guarantees deterministic resolution per Truth Table III - eliminating need for external logic. This is a defining feature of the MASTER IDT7130 architecture.
What is the purpose of the INTL and INTR pins on the 7130LA35PF?
The INTL and INTR pins are active-low interrupt request outputs used for port-to-port communication. Writing to specific addresses (e.g., 3FFh on left port sets INTR; 3FEh on right port sets INTL) triggers these flags, enabling hardware-synchronized handshaking between processors. Their timing is characterized in Table 12a (tINS/tINR = 25 ns max).
Can the 7130LA35PF retain data at 2.0 V, and under what conditions?
Yes, the 7130LA35PF supports data retention at VCC = 2.0 V, as specified in Table 07 ("Data Retention Characteristics"). This mode requires CE > VCC – 0.2 V (i.e., chip disable) and applies only to LA-grade devices. Retention current is ≤4000 µA (MIL/IND) or ≤1500 µA (COM'L) at +25°C.
Is the 7130LA35PF pin-compatible with the IDT7140LA35PF?
No - although both use the FP48 package and share many signal names, the 7130LA35PF has BUSYL/BUSYR as open-drain outputs and INTL/INTR as outputs, whereas the IDT7140LA35PF has BUSYL/BUSYR as inputs and no interrupt generation capability. Pin functions differ fundamentally; they are complementary, not interchangeable.
7130LA35PF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 64-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-TQFP (14x14)
7130LA35PF FAQ
1.How can I place an order for 7130LA35PF through Aetrix?
Please submit a Request for Quotation (RFQ) for 7130LA35PF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7130LA35PF reliable?
The price and inventory of 7130LA35PF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7130LA35PF is usually 5 days.
3.What payment methods are accepted for 7130LA35PF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7130LA35PF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7130LA35PF?
7130LA35PF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7130LA35PF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7130LA35PF?
For technical support, including 7130LA35PF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7130LA35PF requirements.
6.How does Aetrix verify that 7130LA35PF is sourced from the original manufacturer or authorized distributors?
All 7130LA35PF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7130LA35PF meets industry standards.
7.What is the process for return or replacement of 7130LA35PF?
All 7130LA35PF units undergo pre-shipment inspection (PSI). If there is an issue with 7130LA35PF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7130LA35PF part is unused and in its original packaging.
Return procedure for 7130LA35PF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7130LA35PF Tags
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M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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AT24C02C-SSHM-T
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24LC01BT-I/OT
Microchip Technology
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M24C02-FMC6TG
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AT24CS02-SSHM-T
Microchip Technology
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93LC46BT-I/OT
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AT24C04C-SSHM-T
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24LC01BT-I/SN
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24AA02UIDT-I/OT
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AT24C08C-STUM-T
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