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Renesas 7130SA35CB
- Part No.:
- 7130SA35CB
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 48-DIP (0.600", 15.24mm)
- Datasheet:
-
7130SA35CB.pdf
- Description:
- IC SRAM 8KBIT PARALLEL SB48
- Quantity:
- Payment:
- Shipping:
Inventory:3,583
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Product details
Overview
7130SA35CB from IDT is a high-speed 1K × 8 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 35 ns maximum read cycle time, TTL-compatible 5V ±10% supply, and industrial temperature range (–40°C to +85°C). It enables error-free 16-bit-or-wider memory expansion when paired with IDT7140 SLAVE devices in real-time control systems.
For engineers reviewing the 7130SA35CB datasheet, 7130SA35CB pinout, 7130SA35CB application, or 7130SA35CB equivalent, key selection criteria include BUSY arbitration timing (tBAA ≤ 35 ns), dual-port asynchronous access, INT flag support for inter-port signaling, and compatibility with 48-pin ceramic flatpack (FP48) packaging.
Technical Context
The 7130SA35CB implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves port contention via BUSY output flags (BUSYL/BUSYR), requiring external pull-up resistors due to open-drain configuration.
It supports MASTER-only functions including BUSY generation, INT flag assertion, and automatic priority resolution using tAPS (5 ns arbitration priority setup time). The device operates in battery backup mode only in LA variants - the SA suffix confirms standard active/standby power profile (550 mW active, 5 mW standby).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1K × 8 bits (1024 words × 8 data lines) - supports byte-wide parallel access per port |
| Access Time | 35 ns max read cycle (tRC) - guarantees deterministic latency for real-time interrupt response |
| Supply Voltage | 5.0 V ±10% - compatible with legacy TTL and 5V microcontroller buses without level shifting |
| Operating Temp | –40°C to +85°C - qualified for industrial embedded control and motor drive applications |
| Power Consumption | 550 mW typical active, 5 mW typical standby - enables low-heat dissipation in dense PCB layouts |
| Arbitration Logic | On-chip port arbitration with tAPS = 5 ns - eliminates need for external glue logic in multi-CPU systems |
| BUSY Interface | Open-drain BUSYL/BUSYR outputs - requires external pull-up; asserts during write contention to block conflicting writes |
Pinout & Package
7130SA35CB is packaged in a 48-pin ceramic flatpack (FP48), measuring approximately 0.75 in × 0.75 in × 0.11 in, with pins arranged in dual in-line format and index mark at Pin 1 (top-left corner).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 24, 25, 48) | Ground reference | All four GND pins must be connected to system ground plane for stable noise margin and thermal dissipation |
| VCC (Pins 23, 47) | Power supply | Both VCC pins require decoupling capacitors (0.1 µF ceramic + 10 µF tantalum) near package body |
| CEL / CER | Chip enable (left/right) | Active-low enables respective port; CE high places port in TTL-level standby (ISB1 = 25 mA max) |
| OEL / OER | Output enable (left/right) | Active-low controls I/O bus direction; OE high forces I/O pins into high-impedance state |
| R/WL / R/WR | Read/write control (left/right) | High = read, low = write; determines data flow direction on I/O0–I/O7 buses |
| BUSYL / BUSYR | Arbitration status (open-drain) | Low indicates write contention on corresponding port; requires 4.7 kΩ pull-up to VCC |
| INTL / INTR | Interrupt flag (open-drain) | Asserted low to signal inter-port event (e.g., address 3FF writes); also requires pull-up resistor |
| A0L–A9L / A0R–A9R | Address inputs (left/right) | 10-bit address buses support full 1K-word addressing independently per port |
| I/O0L–I/O7L / I/O0R–I/O7R | Data I/O (left/right) | Bidirectional 8-bit data paths; driven by internal drivers during reads, tri-stated during writes unless OE active |
Key Features
| Feature | Design Value |
|---|---|
| On-chip arbitration logic | Resolves simultaneous access conflicts without external logic; uses tAPS = 5 ns to guarantee deterministic priority |
| Dual independent asynchronous ports | Enables concurrent CPU and DMA access to shared memory with no clock synchronization required |
| Open-drain BUSY and INT outputs | Supports wired-OR interrupt aggregation and multi-master BUSY sharing across multiple 7130 devices |
| MASTER-only functionality | Generates BUSY flags and accepts INT clears - essential for building scalable multi-SRAM systems with IDT7140 slaves |
| TTL-compatible interface | Direct connection to 5V microcontrollers, FPGAs, and ASICs without level translators or bus buffers |
Applications
| Motor Control System | Industrial PLC |
|---|---|
Use Scenario: Real-time coordination between motion controller CPU and FPGA-based PWM generator sharing position/velocity data. IC Role / Device Role / Timing Role: 7130SA35CB acts as MASTER dual-port RAM enabling zero-latency data exchange with deterministic BUSY arbitration. Use Value: Eliminates software polling or external semaphores; tBAA ≤ 35 ns ensures sub-microsecond response to position updates. | Use Scenario: Shared memory between main processor and safety-monitoring co-processor in redundant control architecture. IC Role / Device Role / Timing Role: 7130SA35CB provides isolated, conflict-free read/write paths with hardware-enforced write protection via BUSY signals. Use Value: Prevents race conditions during firmware updates; INTL/INTR flags trigger immediate fault logging without CPU overhead. |
| Avionics Data Logger | Test Equipment Controller |
Use Scenario: High-reliability acquisition of sensor streams and timestamped event logs under extended temperature cycling. IC Role / Device Role / Timing Role: 7130SA35CB serves as radiation-tolerant, non-volatile buffer (with external backup) for flight-critical telemetry. Use Value: Industrial temp rating (–40°C to +85°C) and MIL-PRF-38535 QML compliance ensure operation in uncontrolled avionics bays. | Use Scenario: Synchronized waveform capture and pattern generation in automated test equipment with dual-channel D/A and A/D subsystems. IC Role / Device Role / Timing Role: 7130SA35CB bridges test controller and signal processing FPGA, supporting simultaneous stimulus injection and response analysis. Use Value: Asynchronous dual-port operation allows continuous streaming without pipeline stalls; 35 ns access enables >10 MSPS real-time throughput. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C131-35JC | 35 ns access, 1K × 8, but lacks on-chip arbitration logic and BUSY/INT flags; requires external logic for contention management | Suitable for simpler dual-CPU systems without strict real-time arbitration needs | Select when cost sensitivity outweighs need for hardware arbitration and inter-port signaling |
| IDT7140SA35CB | Same speed and pinout, but SLAVE-only: BUSY pins are inputs (not outputs); no arbitration logic; cannot operate standalone | Must be used with 7130SA35CB in MASTER/SLAVE pairs for 16-bit+ bus expansion | Choose only as companion device - not a functional substitute for 7130SA35CB's MASTER capabilities |
Compared with CY7C131-35JC and IDT7140SA35CB, the 7130SA35CB uniquely integrates arbitration, BUSY generation, and INT signaling - enabling self-contained dual-port systems without external logic, while IDT7140SA35CB serves strictly as a scalable extension unit.
Availability
7130SA35CB is available at Aetrix Electronics and suitable for motor control systems, industrial PLCs, avionics data loggers, and automated test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 7130SA35CB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, RF, and sensor solutions, now part of Renesas Electronics.
The IDT7130 product line delivers high-speed dual-port SRAMs designed for deterministic real-time systems where concurrent access, hardware arbitration, and inter-processor communication are critical - especially in industrial automation and aerospace control.
FAQ
What is the maximum operating temperature range for the 7130SA35CB?
The 7130SA35CB is rated for industrial temperature operation from –40°C to +85°C. This specification is confirmed in the Recommended Operating Temperature table (Table 03) and applies across all AC and DC electrical characteristics for the SA speed grade. The device meets this range without derating and is suitable for deployment in harsh industrial environments where ambient temperatures exceed commercial limits.
Does the 7130SA35CB support battery backup data retention?
No, the 7130SA35CB does not support battery backup data retention. That feature is exclusive to LA-suffix variants (e.g., 7130LA35CB), which specify VDR = 2.0 V and ICCDR ≤ 4000 µA under data retention conditions. The "SA" in 7130SA35CB explicitly denotes standard active/standby power operation, with standby current ISB1 = 25 mA (max) at TTL input levels - confirming absence of low-voltage retention circuitry.
How many pins does the 7130SA35CB have, and what package type is used?
The 7130SA35CB uses a 48-pin ceramic flatpack (FP48) package, as documented in Pin Configuration diagrams (Drawing 2689 drw 03F). The FP48 body measures approximately 0.75 in × 0.75 in × 0.11 in. This package is distinct from LCC, DIP, PLCC, and TQFP variants - the "CB" suffix in the part number specifically denotes the ceramic flatpack configuration.
What is the function of the BUSYL and BUSYR pins on the 7130SA35CB?
BUSYL and BUSYR are open-drain arbitration status outputs on the 7130SA35CB. When low, they indicate write contention on the respective left or right port - blocking further writes until the conflict resolves. As stated in Note 1 of the Functional Block Diagram, these outputs require external pull-up resistors. They are outputs only on the MASTER 7130; on SLAVE 7140 devices, these same pins serve as inputs.
Can the 7130SA35CB operate with a 3.3V supply?
No, the 7130SA35CB requires a 5.0 V ±10% supply (4.5 V to 5.5 V), as specified in the Recommended DC Operating Conditions table (Table 02). Its inputs are TTL-compatible (VIH ≥ 2.2 V, VIL ≤ 0.8 V), and its internal circuitry is not characterized for 3.3V operation. Attempting 3.3V supply will result in undefined behavior, failed arbitration, or non-functional BUSY/INT signaling.
7130SA35CB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 48-SIDE BRAZED
7130SA35CB FAQ
1.How can I place an order for 7130SA35CB through Aetrix?
Please submit a Request for Quotation (RFQ) for 7130SA35CB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7130SA35CB reliable?
The price and inventory of 7130SA35CB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7130SA35CB is usually 5 days.
3.What payment methods are accepted for 7130SA35CB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7130SA35CB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7130SA35CB?
7130SA35CB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7130SA35CB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7130SA35CB?
For technical support, including 7130SA35CB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7130SA35CB requirements.
6.How does Aetrix verify that 7130SA35CB is sourced from the original manufacturer or authorized distributors?
All 7130SA35CB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7130SA35CB meets industry standards.
7.What is the process for return or replacement of 7130SA35CB?
All 7130SA35CB units undergo pre-shipment inspection (PSI). If there is an issue with 7130SA35CB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7130SA35CB part is unused and in its original packaging.
Return procedure for 7130SA35CB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7130SA35CB Tags
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M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
Microchip Technology
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AT21CS01-STUM10-T
Microchip Technology
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AT24C02C-SSHM-T
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24LC01BT-I/OT
Microchip Technology
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M24C02-FMC6TG
STMicroelectronics
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AT24CS02-SSHM-T
Microchip Technology
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93LC46BT-I/OT
Microchip Technology
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AT24C04C-SSHM-T
Microchip Technology
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24LC01BT-I/SN
Microchip Technology
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24AA02UIDT-I/OT
Microchip Technology
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AT24C08C-STUM-T
Microchip Technology
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