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Renesas 7133LA35GB
- Part No.:
- 7133LA35GB
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-BPGA
- Datasheet:
-
7133LA35GB.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,093
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Product details
Overview
7133LA35GB from IDT (Integrated Device Technology) is a high-speed 2K × 16-bit dual-port static RAM configured as a MASTER device with on-chip arbitration logic, BUSY output flag, and 35 ns maximum read cycle time. It operates at 5.0 V ±10%, supports independent asynchronous access from left and right ports, and enables 32-bit-or-wider memory expansion when paired with IDT7143 SLAVE devices. It is used in real-time embedded systems requiring concurrent CPU/DSP access to shared memory buffers.
For engineers reviewing the 7133LA35GB datasheet, 7133LA35GB pinout, 7133LA35GB application, or 7133LA35GB equivalent, this page delivers verified technical context, exact timing parameters for contention-aware bus arbitration, battery-backed data retention at 2 V, and validated alternatives for military-grade dual-port SRAM replacement in avionics and radar subsystems.
Technical Context
The 7133LA35GB implements fully asynchronous dual-port operation with separate address, control, and I/O buses per port - enabling simultaneous read/write access without internal synchronization clocks. Its on-chip arbitration logic resolves port-to-port contention by asserting open-drain BUSYL/BUSYR outputs, which require external pull-up resistors and gate write operations on the contending port.
As a MASTER device, it provides BUSY as an output (IDT7143 uses BUSY as input), supports byte-level write enable (R/WLUB/R/WLLB and R/WRUB/R/WRLB), and guarantees tBDD ≤ 35 ns for BUSY-disable-to-valid-data delay under military temperature conditions. It retains data at VCC = 2.0 V with ICCDR ≤ 4000 µA (military grade).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Organization | 2K × 16 bits (32,768 bits total); enables 32-bit word systems via MASTER/SLAVE stacking with IDT7143 |
| Max Read Cycle Time (tRC) | 35 ns - defines minimum interval between successive reads; meets MIL-PRF-38535 QML Class B timing requirements |
| Supply Voltage | 5.0 V ±10% - single-rail TTL-compatible operation; both VCC pins must be connected for reliable function |
| Operating Temperature | –55°C to +125°C - qualified for military applications per MIL-PRF-38535 QML |
| Active Current (ICC) | 240 mA typ. (both ports active, f = fMAX) - low-power LA variant consumes ~100 mW less than SA version |
| Data Retention Voltage | 2.0 V min. - maintains stored data during brown-out; supports battery backup with ≤4000 µA retention current (military) |
| Standby Current (ISB3) | 0.2 mA typ. (full CMOS standby) - enables ultra-low-power hold mode when both CE inputs are high |
Pinout & Package
7133LA35GB is packaged in a 68-pin ceramic PGA (GU68), with identical pinout to IDT7143 devices. The package measures approximately 1.18 in × 1.18 in × 0.16 in and requires connection of both VCC and GND pins for stable operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L / A0R–A10R | Address Inputs (Left/Right Port) | 11-bit address bus per port; selects one of 2K locations independently |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data Bus (Left/Right Port) | 16-bit parallel I/O; high-impedance when OE = VIH or CE = VIH |
| CEL / CER | Chip Enable (Left/Right Port) | Active-low enable; controls port power-down - ISB1/ISB2/ISB3 states depend on CE logic levels |
| R/WLUB / R/WRUB R/WLLB / R/WRLB | Upper/Lower Byte Write Enable | Enables byte-selective writes; allows partial-word updates without read-modify-write cycles |
| OEL / OER | Output Enable (Left/Right Port) | Controls I/O drivers; overrides R/W state for read-only access during write cycles |
| BUSYL / BUSYR | Busy Flag (Output on 7133, Input on 7143) | Open-drain output on 7133LA35GB; signals port contention - requires external pull-up resistor |
Key Features
| Feature | Design Value |
|---|---|
| On-chip port arbitration logic | Resolves simultaneous access to same address without external logic; eliminates "Busy Lock-Out" via MASTER/SLAVE architecture |
| Byte-selectable write control | Independent upper/lower byte enables per port reduce bus turnaround time and simplify partial-word updates |
| Battery backup data retention | Operates down to 2.0 V with guaranteed data hold - supports fail-safe memory preservation during main power loss |
| Open-drain BUSY outputs | Allows wired-OR of multiple BUSY signals for system-level interrupt generation or centralized arbitration control |
| MIL-PRF-38535 QML compliance | Qualified for high-reliability military applications including avionics, radar, and secure comms subsystems |
Applications
| Avionics Flight Control Systems | Radar Signal Processing Units |
|---|---|
Use Scenario: Dual-CPU architecture where flight management computer (FMC) and autopilot controller concurrently access shared navigation state tables. IC Role / Device Role / Timing Role: MASTER 7133LA35GB acts as central memory arbitrator; resolves contention between FMC and autopilot on identical address accesses. Use Value: Eliminates software polling or semaphores; hardware BUSY signaling ensures deterministic <35 ns resolution latency under –55°C to +125°C. |
Use Scenario: Real-time pulse-Doppler radar front-end with DSP and FPGA sharing frame buffer memory for beamforming and clutter filtering. IC Role / Device Role / Timing Role: 7133LA35GB serves as 32-bit-wide memory node (with IDT7143 SLAVE) - left port to FPGA, right port to DSP. Use Value: Asynchronous dual-port access avoids pipeline stalls; 35 ns tRC enables ≥28.5 MHz sustained throughput per port. |
| Tactical Radio Baseband Processors | Military Vehicle Health Monitoring |
Use Scenario: Secure SDR platform with ARM host processor and dedicated crypto co-processor exchanging encrypted packet metadata. IC Role / Device Role / Timing Role: 7133LA35GB provides shared mailbox memory; BUSY logic prevents concurrent write corruption during key exchange handshakes. Use Value: Hardware-enforced atomicity replaces software mutexes; 2 V data retention preserves session keys during brief power interruptions. |
Use Scenario: Armored vehicle ECU logging sensor telemetry (vibration, temp, pressure) while simultaneously serving diagnostic queries from maintenance tablet. IC Role / Device Role / Timing Role: 7133LA35GB stores rolling 2K-sample buffers - left port for sensor acquisition engine, right port for diagnostic readout. Use Value: Independent port timing enables continuous capture at 100 kHz sample rate while supporting non-blocking diagnostic reads at 1 Mbps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C1335KV18-350BZI | 3.3 V core, 1.8 V I/O; 350 MHz DDR interface; no native BUSY arbitration logic | Requires external arbitration logic or FPGA-based conflict resolution; not drop-in for legacy 5 V systems | Choose for new 3.3 V designs needing higher bandwidth; avoid if BUSY-driven deterministic arbitration is required. |
| IDT7143LA35GB | SLAVE-only variant; BUSY pins are inputs only; no on-chip arbitration logic | Must be paired with 7133LA35GB MASTER; cannot operate standalone as arbitration node | Select only when expanding data width beyond 16 bits - e.g., 32-bit systems using one 7133LA35GB + one 7143LA35GB. |
Compared with CY7C1335KV18-350BZI and IDT7143LA35GB, the 7133LA35GB uniquely integrates hardware arbitration and 5 V TTL compatibility - making it irreplaceable in legacy military platforms requiring guaranteed contention resolution without FPGA intervention or voltage translation.
Availability
7133LA35GB is available at Aetrix Electronics and suitable for avionics flight control systems, radar signal processing units, and tactical radio baseband processors requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 7133LA35GB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions, now part of Renesas Electronics.
The IDT7133/7143 product line was designed for real-time embedded systems demanding deterministic memory access - particularly in defense, aerospace, and industrial automation where concurrent multi-processor access and hardware arbitration are critical.
FAQ
What is the difference between 7133LA35GB and 7143LA35GB?
The 7133LA35GB is a MASTER dual-port SRAM with on-chip arbitration logic and open-drain BUSY outputs, while the 7143LA35GB is a SLAVE device with BUSY inputs only and no arbitration capability. The 7133LA35GB can operate standalone or control multiple 7143LA35GB units in width-expanded configurations; the 7143LA35GB must always be paired with a 7133LA35GB to resolve contention.
Does 7133LA35GB support battery backup operation?
Yes, the 7133LA35GB supports battery backup operation with guaranteed data retention at VCC = 2.0 V. In this mode, its data retention current (ICCDR) is ≤4000 µA under military temperature conditions (–55°C to +125°C), enabling fail-safe memory hold during main power loss.
What package type is used for 7133LA35GB?
The 7133LA35GB is supplied in a 68-pin ceramic PGA (GU68) package, measuring approximately 1.18 in × 1.18 in × 0.16 in. It shares identical pinout with IDT7143 devices and requires connection of both VCC and GND pins for reliable operation.
Is 7133LA35GB compliant with military specifications?
Yes, the 7133LA35GB is manufactured in compliance with MIL-PRF-38535 QML, qualified for military temperature range (–55°C to +125°C), and rated for terminal voltage up to +7.0 V. It meets absolute maximum ratings and DC/AC electrical specifications under military-grade test conditions.
How does the BUSY arbitration logic work in 7133LA35GB?
In the 7133LA35GB, BUSY logic asserts BUSYL or BUSYR when both ports attempt access to the same memory location. As a MASTER, it outputs BUSY to stall the contending port's write operation. The BUSY outputs are open-drain and require external pull-up resistors; arbitration priority is resolved in hardware with tAPS = 5 ns setup time.
7133LA35GB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-BPGA
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 68-PGA (29.46x29.46)
7133LA35GB FAQ
1.How can I place an order for 7133LA35GB through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133LA35GB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133LA35GB reliable?
The price and inventory of 7133LA35GB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133LA35GB is usually 5 days.
3.What payment methods are accepted for 7133LA35GB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133LA35GB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133LA35GB?
7133LA35GB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133LA35GB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133LA35GB?
For technical support, including 7133LA35GB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133LA35GB requirements.
6.How does Aetrix verify that 7133LA35GB is sourced from the original manufacturer or authorized distributors?
All 7133LA35GB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133LA35GB meets industry standards.
7.What is the process for return or replacement of 7133LA35GB?
All 7133LA35GB units undergo pre-shipment inspection (PSI). If there is an issue with 7133LA35GB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133LA35GB part is unused and in its original packaging.
Return procedure for 7133LA35GB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133LA35GB Tags
-
M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
Microchip Technology
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AT21CS01-STUM10-T
Microchip Technology
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AT24C02C-SSHM-T
Microchip Technology
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24LC01BT-I/OT
Microchip Technology
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M24C02-FMC6TG
STMicroelectronics
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AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
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24AA02UIDT-I/OT
Microchip Technology
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AT24C08C-STUM-T
Microchip Technology
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