Renesas 7133LA35PF

Overview

7133LA35PF from IDT (Integrated Device Technology) is a high-speed 2K × 16 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 35 ns maximum read cycle time, 2V data retention capability, and TTL-compatible 5V ±10% operation - used in real-time inter-processor communication systems requiring concurrent access without external arbitration logic.

For engineers reviewing the 7133LA35PF datasheet, 7133LA35PF pinout, 7133LA35PF application, or 7133LA35PF equivalent, this page delivers verified timing parameters, byte-selectable write control per port, BUSY arbitration behavior, low-power standby current (1 µA typ.), and package-specific pin mapping for the 68-pin PLCC variant.

Technical Context

The 7133LA35PF implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves simultaneous accesses to identical memory locations by asserting open-drain BUSYL/BUSYR outputs - requiring external pull-up resistors - and gating write signals on the contended port.

It supports battery backup mode at V_CC = 2V with typical data retention current of 100 µA, and features separate upper/lower byte write enables (R/WLUB/R/WLLB and R/WRUB/R/WRLB) enabling partial-word writes without read-modify-write cycles.

Key Specifications

Pinout & Package

7133LA35PF is supplied in a 68-pin Plastic Leaded Chip Carrier (PLCC, package code PLG68), top-view pinout with corner index marker. Both V_CC pins (pins 17 and 43) and both GND pins (pins 26 and 61) must be connected for reliable operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port RAM applications.

Compared with 7133SA35PF, the 7133LA35PF offers 80% lower standby current and 2V data retention - critical for battery-backed systems. Compared with 7143LA35PF, it provides autonomous arbitration and BUSY output capability, enabling stand-alone dual-CPU designs without external logic.

Availability

7133LA35PF is available at Aetrix Electronics and suitable for real-time inter-processor communication, industrial motion control, and avionics data exchange requiring stable component supply, long-term lifecycle support, and MIL/industrial temperature compliance.

Supply support for 7133LA35PF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance memory, timing, and interface solutions, now part of Renesas Electronics.

The IDT7133 family was designed specifically for deterministic, low-latency dual-processor and DSP co-processing applications requiring hardware-managed memory arbitration and battery-backed operation.

FAQ

What is the function of the BUSY pin on the 7133LA35PF?

The BUSY pin on the 7133LA35PF is an open-drain output that signals arbitration contention when both ports attempt simultaneous access to the same memory location. It must be externally pulled up and is used to stall the contended port's write operation. This hardware flag eliminates software polling and ensures deterministic resolution without CPU intervention - a core feature distinguishing the MASTER 7133LA35PF from SLAVE variants.

Does the 7133LA35PF support battery backup operation?

Yes, the 7133LA35PF supports battery backup operation with guaranteed data retention at V_CC = 2V. In this mode, typical data retention current is 100 µA, and the device maintains stored contents indefinitely as long as voltage remains ≥2.0V. This capability is exclusive to LA variants and is validated per IDT specification table 2746 tbl 08 - the 7133LA35PF is explicitly rated for 2V data retention.

What is the difference between 7133LA35PF and 7143LA35PF?

The 7133LA35PF is a MASTER dual-port RAM with on-chip arbitration logic and BUSY output pins, while the 7143LA35PF is a SLAVE device with BUSY input pins only and no arbitration logic. They share identical timing (35 ns), power specs, and pinout, but 7143LA35PF cannot operate stand-alone in contention-prone systems - it requires pairing with a 7133LA35PF in width-expanded configurations. The 7133LA35PF is functionally complete for dual-CPU use; 7143LA35PF is a companion part.

Which package type does the 7133LA35PF use?

The 7133LA35PF uses a 68-pin Plastic Leaded Chip Carrier (PLCC) package, designated PLG68 in IDT documentation. Its body dimensions are approximately 0.95 in × 0.95 in × 0.17 in. Pin 1 is marked by a corner notch, and both V_CC (pins 17, 43) and GND (pins 26, 61) must be connected. This package is RoHS-compliant and qualified for industrial temperature operation.

Can the 7133LA35PF perform partial-word writes?

Yes, the 7133LA35PF supports true partial-word writes via dedicated upper and lower byte write enables: R/WLUB/R/WLLB control the left port's I/O8–I/O15 and I/O0–I/O7, respectively; R/WRUB/R/WRLB do the same for the right port. This allows writing to either byte independently - for example, updating only status flags in the upper byte while preserving data in the lower byte - without requiring read-modify-write sequences or external masking logic.