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Renesas 7133LA90G
- Part No.:
- 7133LA90G
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-BPGA
- Datasheet:
-
7133LA90G.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,782
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Product details
Overview
7133LA90G from IDT (Integrated Device Technology) is a high-speed, low-power 2K × 16 dual-port static RAM designed as a MASTER device with on-chip arbitration logic and open-drain BUSY output. It supports 90 ns max read cycle time, 2V data retention in battery backup mode, and operates across industrial temperature range (–40°C to +85°C) with single 5V ±10% supply. It enables error-free 32-bit+ memory expansion when paired with IDT7143 SLAVE devices in real-time embedded control systems.
For engineers reviewing the 7133LA90G datasheet, 7133LA90G pinout, 7133LA90G application, or 7133LA90G equivalent, this page delivers verified timing parameters (tRC = 90 ns, tAA = 90 ns), power metrics (ISB3 = 0.2 mA typ.), byte-level write control (R/WLUB/R/WLLB), BUSY arbitration behavior, and industrial-grade packaging - all critical for deterministic dual-processor communication, military avionics interlocks, and industrial PLC memory coherency design.
Technical Context
The 7133LA90G implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves port contention by asserting BUSYL/BUSYR flags - open-drain outputs requiring external pull-up resistors - and gating write signals during conflict. The device uses CMOS high-performance technology optimized for low active (1050 mW typ.) and ultra-low standby (1 mW typ.) power.
It supports TTL-compatible signaling, battery backup retention at VCC = 2V, and features separate upper/lower byte write enables per port. Unlike the SLAVE IDT7143, the 7133LA90G provides BUSY as an output and includes internal arbitration priority set-up (tAPS = 5 ns), making it the sole decision point in MASTER/SLAVE width-expansion configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Organization | 2K × 16 (32,768 bits), dual-port SRAM with independent left/right access paths |
| Max Read Cycle Time (tRC) | 90 ns - defines minimum interval between successive reads on same port |
| Active Current (ICC) | 230 mA typ. - total dynamic current draw under full 90 ns cycling with both ports active |
| Full Standby Current (ISB3) | 0.2 mA typ. - ultra-low power state when both CE pins > VCC − 0.2 V and inputs at CMOS levels |
| Data Retention Voltage | 2.0 V min. - guaranteed data hold during battery backup without refresh |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments with no derating |
| Supply Voltage | 4.5 V to 5.5 V - single 5V ±10% rail compatible with legacy TTL logic interfaces |
Pinout & Package
7133LA90G is packaged in a 68-pin PLCC (PLG68) with 0.95″ × 0.95″ footprint. Both VCC pins must be connected to 5V supply and both GND pins to ground for reliable operation. Pin 1 is marked with a corner notch; top-view orientation follows standard PLCC convention.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L | Left Port Address Inputs | 11-bit address bus for left-side memory access (2K = 211) |
| A0R–A10R | Right Port Address Inputs | Independent 11-bit address bus for right-side access |
| I/O0L–I/O15L | Left Port Bidirectional Data | 16-bit data path; direction controlled by R/WLUB/R/WLLB and OEL |
| I/O0R–I/O15R | Right Port Bidirectional Data | 16-bit data path; direction controlled by R/WRUB/R/WRLB and OER |
| CEL / CER | Chip Enable (Left / Right) | Active-low enables respective port; controls automatic power-down into ISB1/ISB2/ISB3 states |
| R/WLUB / R/WRUB | Left/Right Upper Byte Write Enable | Asserted low to enable write to I/O8–I/O15 of respective port |
| R/WLLB / R/WRLB | Left/Right Lower Byte Write Enable | Asserted low to enable write to I/O0–I/O7 of respective port |
| OEL / OER | Output Enable (Left / Right) | Active-low enables output drivers; high-Z when deasserted |
| BUSYL / BUSYR | Busy Flag (Left / Right) | Open-drain outputs (MASTER only); require external pull-up; signal port contention |
Key Features
| Feature | Design Value |
|---|---|
| On-chip port arbitration logic | Resolves simultaneous left/right access to same address without external logic; eliminates "busy lock-out" in multi-chip systems |
| Separate upper/lower byte write control | Enables partial-word writes (8-bit granularity) per port, reducing bus traffic and improving system efficiency |
| 2V data retention mode | Preserves memory contents during main power loss using backup battery; validated at TA = +25°C |
| Ultra-low ISB3 standby current | 0.2 mA typical - enables always-on monitoring subsystems in energy-constrained industrial gateways |
| MASTER/SLAVE width expansion architecture | One 7133LA90G MASTER coordinates arbitration for multiple IDT7143 SLAVEs, enabling seamless 32-bit+ word width without added glue logic |
Applications
| Real-Time Dual-Processor Communication | Military Avionics Interlock Memory |
|---|---|
Use Scenario: Two independent CPUs (e.g., flight control + navigation) share sensor fusion data via shared memory with deterministic latency. IC Role / Device Role / Timing Role: 7133LA90G acts as MASTER dual-port RAM with BUSY arbitration, ensuring atomic read-modify-write cycles and preventing race conditions. Use Value: 90 ns tRC and tAA guarantee sub-100 ns memory access, meeting DO-254 Level A timing budgets for safety-critical avionics. |
Use Scenario: Redundant flight computers exchange status and command vectors through mirrored memory regions with hardware-enforced mutual exclusion. IC Role / Device Role / Timing Role: 7133LA90G provides industrial-temp-rated, MIL-PRF-38535 QML-compliant dual-port storage with open-drain BUSY signaling for fail-safe interlock coordination. Use Value: 2V data retention preserves critical state during brownout; ISB3 = 0.2 mA enables continuous watchdog supervision without battery drain. |
| Industrial PLC Shared Memory Coherency | DSP-Based Motor Control Buffering |
Use Scenario: Programmable Logic Controller CPU and motion coprocessor exchange position setpoints and encoder feedback in hard real-time loop. IC Role / Device Role / Timing Role: 7133LA90G serves as deterministic shared buffer with byte-selectable writes (R/WLUB/R/WLLB), minimizing bus contention during high-frequency I/O updates. Use Value: Separate left/right CE and OE allow independent port gating, enabling precise synchronization with PLC scan cycle and servo update intervals. |
Use Scenario: Digital Signal Processor offloads PWM waveform generation while host microcontroller configures parameters and reads diagnostics. IC Role / Device Role / Timing Role: 7133LA90G functions as low-latency parameter/data exchange buffer with 5V TTL compatibility matching legacy DSP I/O voltage levels. Use Value: 1050 mW active power and 1 mW standby support thermally constrained motor drive enclosures; 68-pin PLCC simplifies PCB layout in space-limited modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT7143LA90G | SLAVE-only variant; BUSY pins are inputs (not outputs); no on-chip arbitration logic | Requires pairing with 7133LA90G MASTER for arbitration; used only in width-expanded systems | Select when building 32-bit+ memory arrays where one 7133LA90G MASTER coordinates multiple SLAVEs |
| Cypress CY7C028V-90AC | 90 ns, 2K × 16 dual-port SRAM; 3.3V core with 5V-tolerant I/O; no built-in BUSY arbitration | Requires external logic or firmware for contention resolution; lacks 2V data retention | Select for 3.3V system integration where external arbitration is acceptable and battery backup is not required |
Compared with IDT7143LA90G and CY7C028V-90AC, the 7133LA90G uniquely integrates MASTER arbitration, open-drain BUSY signaling, and 2V data retention - eliminating external components and enabling self-contained, battery-backed dual-processor coherency in industrial and military designs.
Availability
7133LA90G is available at Aetrix Electronics and suitable for real-time dual-processor communication, military avionics interlock memory, and industrial PLC shared memory coherency requiring stable component supply across extended product lifecycles.
Supply support for 7133LA90G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, memory interface, RF, and sensor solutions, acquired by Renesas Electronics in 2019.
The IDT7133/7143 family was engineered for deterministic, contention-free dual-processor memory sharing in aerospace, defense, and industrial automation - prioritizing hardware arbitration, low-power standby, and battery-backed data integrity.
FAQ
What is the maximum operating speed of the 7133LA90G?
The 7133LA90G has a maximum read cycle time (tRC) of 90 ns, meaning it supports guaranteed access intervals down to 90 ns under industrial temperature conditions (–40°C to +85°C) and 5V ±10% supply. This corresponds to a theoretical maximum throughput of ~11.1 million reads per second per port. The 90 ns rating applies to both address-access (tAA) and chip-enable-access (tACE) timing parameters, confirming deterministic performance in hard real-time systems.
Does the 7133LA90G support battery backup operation?
Yes, the 7133LA90G supports battery backup operation with guaranteed data retention at VCC = 2.0 V minimum. In this mode, the device consumes only 100 µA typical (ICCDR) while preserving all 32,768 bits of memory content. This capability is intrinsic to the LA (low-power) variant and is validated per the datasheet's data retention waveform and tCDR = 0 ns specification - enabling seamless transition to backup power during main supply interruption.
How does the BUSY arbitration logic work in the 7133LA90G?
In the 7133LA90G, BUSY arbitration is implemented as hardware-enforced port contention resolution: when both left and right ports attempt access to the same memory location simultaneously, the on-chip logic asserts BUSYL or BUSYR (open-drain outputs requiring pull-up resistors) to stall the later-arriving access. The winning port proceeds; the stalled port's write is gated internally. This eliminates race conditions without software intervention - a key differentiator from SLAVE-only IDT7143 devices.
What package options are available for the 7133LA90G?
Based on official documentation, the 7133LA90G is offered in 68-pin PLCC (PLG68), 68-pin ceramic PGA (GU68), 68-pin flatpack (FP68), and 100-pin TQFP (PNG100). The "G" suffix in 7133LA90G specifically denotes the 68-pin PLCC package. All variants maintain identical pinouts and electrical specifications; mechanical dimensions and thermal profiles differ per package type - PLCC offers cost-effective reworkability, while TQFP supports higher-density layouts.
Can the 7133LA90G be used without external pull-up resistors on BUSY pins?
No - the BUSYL and BUSYR pins of the 7133LA90G are open-drain outputs and require external pull-up resistors to function correctly. Per the datasheet note: "IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor." Without pull-ups, BUSY signals cannot drive HIGH to indicate non-contention states, breaking arbitration functionality. Typical values range from 4.7 kΩ to 10 kΩ to +5V, balancing rise time and power consumption.
7133LA90G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-BPGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 90ns
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 68-PGA (29.46x29.46)
7133LA90G FAQ
1.How can I place an order for 7133LA90G through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133LA90G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133LA90G reliable?
The price and inventory of 7133LA90G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133LA90G is usually 5 days.
3.What payment methods are accepted for 7133LA90G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133LA90G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133LA90G?
7133LA90G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133LA90G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133LA90G?
For technical support, including 7133LA90G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133LA90G requirements.
6.How does Aetrix verify that 7133LA90G is sourced from the original manufacturer or authorized distributors?
All 7133LA90G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133LA90G meets industry standards.
7.What is the process for return or replacement of 7133LA90G?
All 7133LA90G units undergo pre-shipment inspection (PSI). If there is an issue with 7133LA90G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133LA90G part is unused and in its original packaging.
Return procedure for 7133LA90G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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