Renesas 7133LA90GB

Overview

7133LA90GB from IDT (Integrated Device Technology) is a high-speed 2K × 16 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 90ns maximum read cycle time, 2V data retention capability, and industrial temperature range (–40°C to +85°C). It enables error-free 32-bit-or-wider memory expansion when paired with IDT7143 SLAVE devices in real-time embedded control systems requiring concurrent access from two independent processors.

For engineers reviewing the 7133LA90GB datasheet, 7133LA90GB pinout, 7133LA90GB application, or 7133LA90GB equivalent, this page delivers verified timing parameters, byte-selectable write control per port, BUSY arbitration behavior, battery backup operation support, and package-specific layout guidance for reliable dual-processor memory interfacing.

Technical Context

The 7133LA90GB implements fully asynchronous dual-port operation with separate address, control, and I/O buses for left and right ports - enabling simultaneous, independent read/write access to any memory location. Its on-chip arbitration logic resolves contention via open-drain BUSYL/BUSYR outputs that require external pull-up resistors.

As a MASTER device, it generates BUSY flags during address-matching contention and supports width expansion with IDT7143 SLAVE parts using CE- or address-controlled arbitration. The LA variant delivers ultra-low standby current (1 µA typ.) and retains data at VCC = 2V, making it suitable for battery-backed applications.

Key Specifications

Pinout & Package

7133LA90GB is packaged in a 68-pin PLCC (PLG68) with 0.05-inch lead pitch, body size ≈ 0.95 in × 0.95 in × 0.17 in. Both VCC and GND pins must be connected for reliable operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with IDT7143LA90GB and CY7C1371DV33-90BGXI, the 7133LA90GB uniquely integrates MASTER arbitration logic and 2V data retention in a 5V-compatible 68-pin PLCC package - making it irreplaceable for industrial systems requiring deterministic contention handling and battery-backed state preservation without voltage translation.

Availability

7133LA90GB is available at Aetrix Electronics and suitable for industrial motion control, avionics data buffering, and medical imaging frame store applications requiring stable component supply, long-term lifecycle support, and guaranteed MIL-PRF-38535 QML compliance.

Supply support for 7133LA90GB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance memory, timing, and interface solutions for communications, computing, and industrial markets.

The IDT7133/7143 family was designed specifically for real-time dual-processor systems requiring deterministic, hardware-arbitrated shared memory - targeting aerospace, medical, and factory automation applications demanding zero-software-overhead concurrency control.

FAQ

What is the function of the BUSY pins on the 7133LA90GB?

The BUSYL and BUSYR pins on the 7133LA90GB are open-drain outputs indicating address contention between ports. When both ports attempt access to the same memory location, the 7133LA90GB asserts BUSY to stall the lower-priority port. These pins require external pull-up resistors and are used exclusively in MASTER mode - unlike the SLAVE IDT7143 where BUSY is an input.

Does the 7133LA90GB support true 32-bit data bus expansion?

Yes - the 7133LA90GB is explicitly designed as a MASTER device to coordinate with IDT7143 SLAVE parts for seamless 32-bit-or-wider memory expansion. In such configurations, the 7133LA90GB provides arbitration and BUSY signaling while SLAVE devices respond to its BUSY input, eliminating "busy lock-out" and enabling full-speed operation without external logic.

What is the significance of the 'LA' suffix in 7133LA90GB?

The 'LA' in 7133LA90GB denotes the Low-Power Active/Standby variant: it consumes 1050 mW typical active power and only 1 µA typical full-standby current (ISB3), versus 1150 mW/5 µA for the SA version. Crucially, LA parts also support 2V data retention - enabling battery backup operation not available in SA variants.

Can the 7133LA90GB operate reliably at –40°C?

Yes - the 7133LA90GB is qualified for the industrial temperature range of –40°C to +85°C. This rating is explicitly confirmed in the datasheet's "Maximum Operating Temperature and Supply Voltage" table and applies to all speed grades including the 90ns version. It meets MIL-PRF-38535 QML requirements for enhanced reliability.

How does the 7133LA90GB handle simultaneous writes to the same address?

The 7133LA90GB uses on-chip arbitration logic to detect simultaneous writes to identical addresses. It grants access to the port that asserts its chip enable (CE) or address first, while asserting BUSY on the contending port to inhibit the write. This hardware resolution eliminates race conditions and guarantees deterministic behavior without software intervention.