Renesas 7133LA90J

Overview

7133LA90J from IDT (Integrated Device Technology) is a high-speed 2K × 16 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 90ns maximum read cycle time, 2V data retention capability, and industrial temperature range (–40°C to +85°C). It enables error-free 32-bit-or-wider memory expansion when paired with IDT7143 SLAVE devices in real-time embedded control systems.

For engineers reviewing the 7133LA90J datasheet, 7133LA90J pinout, 7133LA90J application, or 7133LA90J equivalent, this page delivers verified timing parameters, byte-selectable write control per port, BUSY arbitration behavior, low-power standby current (1 µA typ.), and package-specific pin validation for 68-pin PLCC.

Technical Context

The 7133LA90J implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves simultaneous access to identical memory locations by asserting open-drain BUSYL/BUSYR outputs - requiring external pull-up resistors - and gating write signals on the contended port.

It supports battery backup via 2V data retention mode, where CE > V_HC places the device in ultra-low-power state (ICCDR ≤ 4000 µA max at MIL/IND), and features separate upper/lower byte write enables (R/WLUB/R/WLLB and R/WRUB/R/WRLB) for granular 8-bit writes per port.

Key Specifications

Pinout & Package

7133LA90J is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC), with body dimensions ≈ 0.95 in × 0.95 in × 0.17 in. Both VCC and GND pins must be connected to ensure reliable operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with IDT7143LA90J and CY7C133-100AXC, the 7133LA90J uniquely integrates master arbitration, open-drain BUSY signaling, and 2V data retention - making it the only choice for self-contained, fault-resilient dual-CPU memory sharing in industrial and avionics systems.

Availability

7133LA90J is available at Aetrix Electronics and suitable for real-time industrial PLCs, digital signal processing buffers, military avionics data loggers, and redundant communication controllers requiring stable component supply across extended product lifecycles.

Supply support for 7133LA90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, memory interface, RF, and sensor solutions, acquired by Renesas Electronics in 2019.

The IDT7133/7143 family was designed specifically for deterministic, contention-free dual-processor memory sharing in industrial automation, aerospace, and telecom infrastructure - emphasizing hardware arbitration, low-power retention, and wide temperature operation.

FAQ

What is the function of the BUSY pins on the 7133LA90J?

The BUSYL and BUSYR pins on the 7133LA90J are open-drain outputs that signal port contention when both left and right ports attempt simultaneous access to the same memory location. They require external pull-up resistors and gate write operations on the contended port to prevent data corruption. This hardware arbitration eliminates the need for software semaphores in dual-CPU systems.

Does the 7133LA90J support true 2V data retention, and what current does it draw in that mode?

Yes, the 7133LA90J supports guaranteed 2V data retention per specification table 2746 tbl 08. In this mode, with CE > V_HC and inputs at CMOS levels, it draws ≤4000 µA at industrial temperature (–40°C to +85°C) and ≤1500 µA at commercial temperature - enabling robust battery-backup operation without external regulators.

Can the 7133LA90J operate as a standalone dual-port RAM without a SLAVE device?

Yes, the 7133LA90J functions fully as a standalone 2K × 16 dual-port SRAM with independent left/right access, byte-selectable writes, and on-chip arbitration. The SLAVE (IDT7143) is required only when expanding data bus width beyond 16 bits - e.g., to 32 or 64 bits - using the MASTER/SLAVE architecture.

What is the significance of the 'LA' suffix in 7133LA90J?

The 'LA' suffix denotes the Low-Power Active/Standby variant of the IDT7133 family. Compared to 'SA' (Standard Active), the 7133LA90J delivers 1050 mW typical active power and only 1 mW typical standby power - a 5× reduction in standby consumption - achieved through optimized CMOS design and enhanced power-down circuitry.

How are the two VCC and two GND pins used in the 68-pin PLCC package of the 7133LA90J?

Both VCC pins (pins 17 and 44) and both GND pins (pins 26 and 35) in the 68-pin PLCC package must be connected to their respective supply rails. This dual-power/dual-ground configuration reduces impedance, minimizes switching noise, and ensures timing compliance across the full industrial temperature range - as explicitly required in datasheet notes.