Renesas 7133LA90JI

Overview

7133LA90JI from IDT is a high-speed 2K × 16 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 90 ns maximum read cycle time, 2V data retention capability, and industrial temperature range (–40°C to +85°C). It enables error-free 32-bit-or-wider memory expansion when paired with IDT7143 SLAVE devices in real-time embedded control systems requiring concurrent CPU and DMA access.

For engineers reviewing the 7133LA90JI datasheet, 7133LA90JI pinout, 7133LA90JI application, or 7133LA90JI equivalent, key selection criteria include BUSY arbitration timing (tBDD ≤ 40 ns), low standby current (ISB3 = 0.2 mA typ.), battery backup support, and compatibility with 68-pin PLCC packaging for legacy military/industrial PCB layouts.

Technical Context

The 7133LA90JI implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves port contention by asserting open-drain BUSYL/BUSYR outputs-requiring external pull-up resistors-and supports MASTER-only arbitration in width-expanded configurations.

It features separate upper/lower byte write enables (R/WLUB/R/WLLB and R/WRUB/R/WRLB), TTL-compatible 5V ±10% single-supply operation, and automatic power-down via chip enable (CE) with four distinct standby modes (ISB1–ISB4), enabling ultra-low-power battery-backed data retention at VCC = 2V.

Key Specifications

Pinout & Package

68-pin Plastic Leaded Chip Carrier (PLCC) package with 0.050" lead pitch, body size ≈ 0.95" × 0.95" × 0.17", dual VCC and GND pins requiring parallel connection for stable operation per datasheet Note 1 & 2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with CY7C1335KV18-90BZI and IDT7143LA90JI, the 7133LA90JI uniquely delivers integrated hardware arbitration, battery-backed retention, and industrial temperature operation in a single 68-pin PLCC package-making it irreplaceable for deterministic real-time embedded memory subsystems where external logic must be minimized.

Availability

7133LA90JI is available at Aetrix Electronics and suitable for industrial motion control, avionics data buffering, and medical imaging frame store applications requiring stable component supply, long-term lifecycle support, and traceable sourcing for safety-critical designs.

Supply support for 7133LA90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, RF, and power management ICs, now part of Renesas Electronics.

The IDT7133/7143 product line was designed specifically for deterministic dual-processor and real-time embedded systems requiring concurrent, contention-free memory access-targeting industrial automation, aerospace, and telecom infrastructure.

FAQ

What is the function of the BUSY pins on the 7133LA90JI?

The BUSYL and BUSYR pins on the 7133LA90JI are open-drain arbitration outputs that assert low when port contention occurs on the corresponding port. As a MASTER device, the 7133LA90JI uses these signals to stall conflicting writes-preventing data corruption. External pull-up resistors are mandatory per datasheet Note 1. The 7133LA90JI does not accept BUSY as an input; that function belongs to the SLAVE IDT7143LA90JI.

Does the 7133LA90JI support true 2V operation or only data retention at 2V?

The 7133LA90JI supports full functional operation at VCC = 4.5 V to 5.5 V. At 2V, it enters data retention mode only-where the memory array preserves stored data but all control logic, I/O drivers, and arbitration are disabled. This mode draws ≤4000 µA (MIL/IND) and is intended solely for backup power scenarios, not active read/write cycles.

Can the 7133LA90JI be used without the BUSY arbitration feature?

Yes-the 7133LA90JI can operate without BUSY arbitration by tying both BUSYL and BUSYR pins HIGH via pull-up resistors and ensuring mutually exclusive address access in firmware. However, this eliminates hardware-enforced contention resolution, making the system vulnerable to data corruption if software coordination fails. The arbitration logic remains active but has no effect unless BUSY is connected to external logic.

What is the difference between the SA and LA versions of the 7133 series?

The LA version (e.g., 7133LA90JI) is the low-power variant: it consumes 1050 mW typical active power vs. 1150 mW for SA, and achieves 1 mW typical standby (ISB3 = 0.2 mA) versus 5 mW for SA. Crucially, only LA parts support 2V data retention-SA parts lose data below VCC = 4.5 V. Both share identical timing, pinout, and functionality otherwise.

Is the 7133LA90JI pin-compatible with the 7133SA90JI?

Yes-the 7133LA90JI and 7133SA90JI are fully pin-compatible and share identical 68-pin PLCC footprint, timing specifications (90 ns), and functional behavior. The only differences are power consumption and data retention capability. A direct PCB-level replacement is possible, though system-level validation of thermal and power delivery margins is recommended due to differing ICC and ISB characteristics.