Renesas 7133SA20G

Overview

7133SA20G from IDT (Integrated Device Technology) is a high-speed 2K × 16-bit dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 20 ns maximum read cycle time, TTL-compatible 5V ±10% operation, and open-drain BUSY output requiring external pull-up. It enables error-free 32-bit+ memory expansion when paired with IDT7143 SLAVE devices in real-time embedded control systems.

For engineers reviewing the 7133SA20G datasheet, 7133SA20G pinout, 7133SA20G application, or 7133SA20G equivalent, this page delivers verified timing parameters, byte-select write control, battery-backed data retention capability (2V), industrial temperature support (–40°C to +85°C), and precise port-to-port arbitration behavior critical for deterministic multi-CPU memory access.

Technical Context

The 7133SA20G implements fully asynchronous dual-port architecture with independent left/right address, control, and I/O buses - enabling simultaneous read/write operations without internal synchronization clocks. Its on-chip arbitration logic resolves contention by asserting BUSYL/BUSYR flags when both ports access the same memory location, with priority determined by tAPS (5 ns arbitration priority setup time).

As a MASTER device, it features open-drain BUSY outputs (requiring external pull-up), supports separate upper/lower byte write enables (R/WLUB/R/WLLB and R/WRUB/R/WRLB), and provides full 2K × 16-bit memory mapping across two independent 11-bit address spaces (A0L–A10L and A0R–A10R). It operates in commercial and industrial temperature grades with 20 ns max access at 5V.

Key Specifications

Pinout & Package

7133SA20G is packaged in a 68-pin PLCC (PLG68) with 0.95″ × 0.95″ footprint and 0.17″ height. Pin layout supports dual independent ports: left port (L) and right port (R), each with dedicated address, data, and control signals. Both VCC and GND pins must be connected for reliable operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with CY7C024AV-20AXC, 7133SA20G delivers integrated arbitration and deterministic BUSY signaling - eliminating external logic and reducing PCB area. Against IDT7143SA20G, it provides full MASTER functionality including open-drain BUSY output and arbitration priority setup, making it the sole choice for standalone dual-port control applications.

Availability

7133SA20G is available at Aetrix Electronics and suitable for industrial motion controllers, avionics display buffers, and medical imaging pipelines requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature performance.

Supply support for 7133SA20G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology) was a fabless semiconductor company specializing in high-performance memory, timing, and interface solutions before its acquisition by Renesas Electronics in 2019.

The IDT7133 family was engineered specifically for deterministic dual-CPU memory sharing in real-time embedded systems - emphasizing hardware arbitration, low-latency access, and robust industrial-grade reliability.

FAQ

What is the function of the BUSY pin on the 7133SA20G?

The BUSY pin on the 7133SA20G is an open-drain output that signals memory contention when both ports attempt to access the same address simultaneously. As a MASTER device, it asserts BUSYL or BUSYR to stall the contending port's write operation until resolution. External pull-up resistors are mandatory for proper logic-level operation, and the timing is governed by parameters like tBAA (20 ns max BUSY access time from address).

Can the 7133SA20G operate in battery backup mode?

Yes, the 7133SA20G supports battery backup operation with data retention down to 2.0 V (VDR), maintaining stored contents during main power loss. This is confirmed in the LA variant's specifications, and the SA variant shares identical retention capability. The typical data retention current is 100 µA at 2 V, enabling reliable operation with coin-cell or supercapacitor backup sources.

How does the 7133SA20G differ from the IDT7143SA20G?

The 7133SA20G is a MASTER dual-port RAM with on-chip arbitration logic and open-drain BUSY outputs, while the IDT7143SA20G is a SLAVE device with BUSY inputs only and no arbitration circuitry. They share identical pinouts and timing, but 7133SA20G can operate standalone; IDT7143SA20G requires pairing with a 7133SA20G for width expansion and cannot resolve contention autonomously.

What package options are available for the 7133SA20G?

The 7133SA20G is offered in multiple packages: 68-pin ceramic PGA (GU68), 68-pin flatpack (FP68), 68-pin PLCC (PLG68), and 100-pin TQFP (PNG100). The "G" suffix in 7133SA20G specifically denotes the 68-pin PLCC (PLG68) package, which measures approximately 0.95″ × 0.95″ × 0.17″ and is preferred for industrial applications due to thermal and mechanical robustness.

Does the 7133SA20G support independent byte write control?

Yes, the 7133SA20G provides separate upper and lower byte write enables for both ports: R/WLUB and R/WLLB for the left port, R/WRUB and R/WRLB for the right port. This allows granular 8-bit writes to I/O0–I/O7 (lower byte) or I/O8–I/O15 (upper byte), preventing unintended modification of adjacent bytes during partial-word updates - critical for register-mapped peripheral interfaces.