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Renesas 7133SA20PF
- Part No.:
- 7133SA20PF
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 100-LQFP
- Datasheet:
-
7133SA20PF.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,571
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Product details
Overview
7133SA20PF from IDT is a high-speed 2K × 16 dual-port static RAM with master arbitration logic, 20 ns max read cycle time, TTL-compatible 5V ±10% operation, and industrial temperature range (–40°C to +85°C). It enables simultaneous asynchronous access from two independent ports and supports 32-bit+ bus expansion when paired with IDT7143 slave devices in real-time control systems.
For engineers reviewing the 7133SA20PF datasheet, 7133SA20PF pinout, 7133SA20PF application, or 7133SA20PF equivalent, this page delivers verified timing parameters, byte-selectable write control per port, BUSY arbitration behavior, power-down modes, and package-specific layout guidance for 68-pin PLCC implementation.
Technical Context
The 7133SA20PF implements fully asynchronous dual-port architecture with separate address, control, and I/O buses for left and right ports. Its on-chip arbitration logic resolves contention when both ports access the same memory location, asserting open-drain BUSYL/BUSYR outputs to stall conflicting writes.
It supports independent lower/upper byte write enable (R/WLLB/R/WLUB and R/WRLB/R/WRUB), output enable per port (OEL/OER), and chip-enable–controlled power-down. Data retention at 2V is supported only in LA variants; the SA variant prioritizes speed over battery backup.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Organization | 2K × 16 (32,768 bits), dual-port SRAM with independent left/right addressing |
| Max Read Cycle Time | 20 ns - defines minimum clock-to-data latency in real-time DSP or FPGA co-processor interfaces |
| Supply Voltage | 5.0 V ±10% - compatible with legacy 5V TTL logic families without level-shifting |
| Operating Temperature | –40°C to +85°C - qualified for industrial embedded control and motor drive applications |
| Active Current (Typ.) | 250 mA - determines thermal design margin and regulator sizing for continuous dual-port operation |
| Standby Current (Typ.) | 25 mA - enables low-power idle states during CPU wait cycles or inter-frame gaps |
| Package | 68-pin PLCC (PLG68) - surface-mount compatible with standard reflow profiles and IPC-7351 land patterns |
Pinout & Package
7133SA20PF is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC, code PLG68), with dual-row gull-wing leads, body size ≈ 0.95 in × 0.95 in × 0.17 in. Both VCC and GND pins must be connected for reliable operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L / A0R–A11R | Address Inputs (Left/Right) | 11-bit address per port selects one of 2K locations; independent decoding enables concurrent access |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data Bus (Left/Right) | 16-bit parallel data path per port; high-impedance state during CE=VIH or OE=VIH |
| CEL / CER | Chip Enable (Left/Right) | Active-low enable for port-specific power-down; deassertion places port in standby (ISB1 mode) |
| R/WLUB / R/WRUB R/WLLB / R/WRLB | Upper/Lower Byte Write Enable (Left/Right) | Enables byte-granular writes - critical for mixed-endian or partial-register updates without read-modify-write |
| OEL / OER | Output Enable (Left/Right) | Controls tri-state output drivers; allows shared bus usage with other peripherals |
| BUSYL / BUSYR | Busy Flag (Open-Drain Output) | Indicates port contention; requires external pull-up; used to stall CPU or DMA on conflict |
Key Features
| Feature | Design Value |
|---|---|
| On-chip arbitration logic | Resolves simultaneous access to identical addresses without external logic - eliminates race conditions in multi-CPU systems |
| Separate upper/lower byte write control | Enables atomic 8-bit updates to 16-bit registers - avoids corruption during partial writes in communication protocol stacks |
| Open-drain BUSY outputs with priority resolution | Allows wired-OR of multiple BUSY signals for system-level interrupt generation on any port conflict |
| Asynchronous dual-port operation | Permits independent clock domains (e.g., FPGA fabric clock vs. microcontroller bus clock) without synchronization overhead |
| 68-pin PLCC and TQFP packaging options | Supports both through-hole prototyping (PLCC) and high-density SMT production (TQFP) with identical pinout |
Applications
| Industrial Motion Controller | FPGA Co-Processor Buffer |
|---|---|
Use Scenario: Real-time servo loop running at 20 kHz synchronizes position feedback (Port A) and command updates (Port B) in a CNC axis controller. IC Role / Device Role / Timing Role: Dual-port RAM acts as zero-latency handshake buffer between motion ASIC and host processor; 20 ns tRC ensures sub-microsecond data exchange. Use Value: Eliminates FIFO depth uncertainty and pipeline stalls - guarantees deterministic jitter < 100 ns across all operating temperatures. |
Use Scenario: High-speed image preprocessing pipeline where FPGA processes pixel blocks while ARM core manages metadata and frame buffering. IC Role / Device Role / Timing Role: 7133SA20PF serves as ping-pong frame buffer; left port handles DMA writes, right port feeds FPGA read requests with no arbitration delay. Use Value: Enables full-bandwidth 16-bit pixel streaming at >50 MB/s without external arbitration logic or clock domain crossing circuits. |
| Avionics Data Concentrator | Digital Signal Analyzer |
Use Scenario: ARINC 429 receiver module aggregates sensor inputs and forwards time-stamped packets to flight management system via shared memory. IC Role / Device Role / Timing Role: Acts as contention-managed mailbox between safety-critical sensor interface (Port A) and certified host processor (Port B); BUSY logic prevents packet overwrite. Use Value: Meets DO-254 Level A timing assurance requirements by guaranteeing atomic 16-bit word transfers under worst-case contention. |
Use Scenario: Real-time spectrum analysis system captures RF samples at 100 MSPS and performs FFT in bursts, requiring rapid data handoff between ADC interface and DSP engine. IC Role / Device Role / Timing Role: Provides non-blocking dual-port access for ADC DMA (left) and FFT accelerator (right); 20 ns access enables 50 MHz effective throughput per port. Use Value: Achieves sustained 80 MB/s aggregate bandwidth - 2× faster than single-port SRAM with external glue logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C133-25JC | 25 ns max access, 5V-only, no built-in arbitration logic - requires external BUSY management | Lacks master/slave expansion capability; limited to standalone 2K×16 use | Select when cost sensitivity outweighs need for automatic contention resolution |
| IDT7143SA20PF | Identical speed/package but functions as SLAVE only - BUSY pin is input-only, no arbitration logic | Used exclusively with 7133SA20PF in 32-bit+ bus expansion; cannot operate stand-alone as master | Required companion part for width expansion; not a functional substitute for 7133SA20PF |
Compared with CY7C133-25JC, 7133SA20PF integrates arbitration and eliminates external logic; compared with IDT7143SA20PF, it provides autonomous master control and BUSY output - making it the sole choice for self-contained dual-port systems.
Availability
7133SA20PF is available at Aetrix Electronics and suitable for industrial motion control, avionics data concentrators, FPGA co-processor buffers, and digital signal analyzers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 7133SA20PF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance memory, timing, and interface solutions for communications, computing, and industrial markets.
The IDT7133/7143 family was designed specifically for real-time embedded systems requiring deterministic dual-port memory access - targeting applications where CPU-to-peripheral handshaking latency must be bounded and predictable.
FAQ
What is the maximum guaranteed read cycle time for 7133SA20PF?
The 7133SA20PF has a maximum guaranteed read cycle time (tRC) of 20 ns under commercial temperature conditions (0°C to +70°C) and 5.0 V ±10% supply. This specification is production-tested and applies to both ports independently, enabling deterministic timing in hard real-time systems where worst-case latency must be bounded.
Does 7133SA20PF support battery backup data retention?
No, the 7133SA20PF does not support battery backup data retention. That feature is exclusive to the LA variant (e.g., 7133LA20PF), which specifies 2 V data retention voltage and typical 100 µA retention current. The SA suffix denotes high-speed, standard-power operation optimized for performance over low-voltage holdover.
How is BUSY arbitration implemented in 7133SA20PF?
The 7133SA20PF implements hardware arbitration using open-drain BUSYL and BUSYR outputs that assert when both ports attempt simultaneous access to the same memory location. The device internally grants priority based on address match timing and tAPS setup; the losing port's write is gated, and its BUSY signal must be externally pulled up to function correctly.
Can 7133SA20PF operate in a 32-bit data bus configuration?
Yes - the 7133SA20PF is explicitly designed as a MASTER device for bus width expansion. When paired with one or more IDT7143SLAVE devices sharing the same address space, it enables seamless 32-bit or wider data paths using its dedicated BUSY output to coordinate write operations across multiple chips without external logic.
What package type is used for 7133SA20PF?
The 7133SA20PF uses a 68-pin Plastic Leaded Chip Carrier (PLCC) package, designated PLG68. Its dimensions are approximately 0.95 in × 0.95 in × 0.17 in, and it requires connection of both VCC and GND pins for reliable operation - as specified in the official IDT documentation for this variant.
7133SA20PF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 100-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 20ns
- Access Time:
- 20 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TQFP (14x14)
7133SA20PF FAQ
1.How can I place an order for 7133SA20PF through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA20PF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA20PF reliable?
The price and inventory of 7133SA20PF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA20PF is usually 5 days.
3.What payment methods are accepted for 7133SA20PF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA20PF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA20PF?
7133SA20PF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA20PF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA20PF?
For technical support, including 7133SA20PF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA20PF requirements.
6.How does Aetrix verify that 7133SA20PF is sourced from the original manufacturer or authorized distributors?
All 7133SA20PF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA20PF meets industry standards.
7.What is the process for return or replacement of 7133SA20PF?
All 7133SA20PF units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA20PF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA20PF part is unused and in its original packaging.
Return procedure for 7133SA20PF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA20PF Tags
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