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Renesas 7133SA35GB
- Part No.:
- 7133SA35GB
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-BPGA
- Datasheet:
-
7133SA35GB.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,949
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Product details
Overview
7133SA35GB from IDT is a high-speed 2K × 16-bit dual-port static RAM configured as a MASTER device with on-chip arbitration logic, BUSY output flag (open-drain), and separate upper/lower byte write controls per port. It supports 35 ns max read cycle time, operates at 5.0 V ±10%, and enables error-free 32-bit+ bus expansion when paired with IDT7143 SLAVE devices in industrial/military systems.
For engineers reviewing the 7133SA35GB datasheet, 7133SA35GB pinout, 7133SA35GB application, or 7133SA35GB equivalent, this page delivers verified timing specs (tRC = 35 ns, tAA = 35 ns), power data (1150 mW active typ., 5 mW standby typ.), dual-port arbitration behavior, battery backup capability (2 V data retention), and exact 68-pin PLCC package mapping - all critical for real-time embedded memory co-processor designs.
Technical Context
The 7133SA35GB implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves simultaneous access to identical memory locations by asserting BUSYL/BUSYR outputs, enabling deterministic priority resolution without external logic.
As a MASTER device, it features open-drain BUSY outputs requiring pull-up resistors, while supporting TTL-compatible signaling, single 5 V supply, and automatic power-down via CE-controlled standby mode. The SA suffix denotes standard-power operation (vs. LA low-power variant) with industrial/military temperature support (–40°C to +85°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2,048 × 16 bits (32 KB total); supports independent concurrent read/write on two ports |
| Access Time (max) | 35 ns read cycle (tRC); defines minimum time between successive reads on same port |
| Supply Voltage | 4.5 V to 5.5 V; single-rail operation compatible with legacy 5 V TTL/CMOS systems |
| Operating Temperature | –40°C to +85°C; qualified for industrial applications per datasheet grade specification |
| Active Power (typ.) | 1150 mW; determines thermal budget and heatsink requirements in dense memory subsystems |
| Standby Current (typ.) | 5 mA (ISB1); enables low-power sleep modes during CPU idle cycles without data loss |
| Data Retention | 2 V minimum VCC; allows battery-backed operation during main power failure |
Pinout & Package
7133SA35GB is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC), with dual-row gull-wing leads, body size ≈ 0.95 in × 0.95 in × 0.17 in. Both VCC and GND pins must be connected for reliable operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L / A0R–A10R | Address Inputs (Left/Right) | 11-bit address per port selects one of 2K locations; independent addressing enables true concurrency |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data (Left/Right) | 16-bit parallel data path per port; supports byte-level writes via R/WLUB/R/WLLB and R/WRUB/R/WRLB |
| CEL / CER | Chip Enable (Left/Right) | Active-low enables port access; deassertion forces port into low-power standby (ISB1/ISB2) |
| R/WLUB / R/WRUB | Upper Byte Write Enable (L/R) | Controls write to I/O8–I/O15; enables partial-word writes without disturbing lower byte |
| R/WLLB / R/WRLB | Lower Byte Write Enable (L/R) | Controls write to I/O0–I/O7; complements upper-byte control for granular 8-bit updates |
| OEL / OER | Output Enable (Left/Right) | Active-low enables data output drivers; high-impedance state prevents bus contention |
| BUSYL / BUSYR | Busy Flag (Open-Drain Output) | Asserted when port contention occurs; requires external pull-up; used for hardware arbitration stall |
Key Features
| Feature | Design Value |
|---|---|
| On-chip port arbitration logic | Resolves simultaneous access to identical addresses without external logic or software intervention |
| Separate upper/lower byte write control | Enables atomic 8-bit writes per port, avoiding read-modify-write cycles for partial-word updates |
| Open-drain BUSY outputs with priority arbitration | Allows wired-OR of multiple BUSY signals for system-level interrupt generation on contention events |
| 2 V data retention mode | Maintains memory contents during main power loss using backup battery, critical for fault-tolerant systems |
| MASTER/SLAVE expandability | Supports seamless 32-bit+ data bus width expansion using IDT7143 SLAVE devices without added glue logic |
Applications
| Real-Time Digital Signal Processing | Industrial Motion Control |
|---|---|
Use Scenario: Dual-CPU architecture where DSP handles algorithm execution while microcontroller manages I/O and safety monitoring. IC Role / Device Role / Timing Role: 7133SA35GB serves as shared memory buffer with deterministic arbitration, enabling zero-latency inter-processor communication. Use Value: 35 ns access time ensures sub-microsecond data exchange; BUSY logic prevents race conditions during simultaneous FFT coefficient updates and motor command writes. |
Use Scenario: CNC machine controller synchronizing servo position feedback (Port A) with trajectory planning commands (Port B). IC Role / Device Role / Timing Role: Acts as dual-port scratchpad memory with hardware-enforced write ordering across motion axes. Use Value: On-chip arbitration eliminates need for external semaphores; 2 V data retention preserves last known safe position during brownout events. |
| Military Avionics Data Fusion | Telecom Packet Buffering |
Use Scenario: Radar and ESM subsystems sharing target track data in MIL-STD-1553B-equipped platform. IC Role / Device Role / Timing Role: MASTER 7133SA35GB coordinates memory access between sensor processors operating at different clock domains. Use Value: –40°C to +85°C rating ensures reliability in environmental chambers; 35 ns timing meets real-time tracking latency budgets. |
Use Scenario: Line card buffering incoming/outgoing Ethernet frames in carrier-grade switch ASIC interface. IC Role / Device Role / Timing Role: Provides non-blocking dual-port access for ingress parser and egress scheduler engines. Use Value: Separate byte write enables header modification without rewriting full packet; 1150 mW active power fits within thermal envelope of dense line cards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT7143SA35GB | SLAVE-only variant; BUSY pins are inputs (not outputs); no on-chip arbitration logic | Used only in width-expanded systems with 7133SA35GB as MASTER; cannot operate stand-alone as arbitrator | Select when building 32-bit+ memory arrays requiring hardware arbitration offload to a single MASTER |
| CY7C133-35JC | Cypress part; 68-pin PLCC; 35 ns access; no BUSY arbitration - uses semaphore register instead | Lacks hardware BUSY signaling; requires software-managed mutual exclusion or external logic for contention resolution | Choose if system already implements semaphore-based coherency and avoids open-drain BUSY routing complexity |
Compared with IDT7143SA35GB and CY7C133-35JC, the 7133SA35GB uniquely provides integrated hardware arbitration and open-drain BUSY outputs - eliminating software overhead and external logic in real-time dual-processor systems requiring deterministic memory access control.
Availability
7133SA35GB is available at Aetrix Electronics and suitable for industrial motion control, military avionics, real-time DSP, and telecom packet buffering applications requiring stable component supply, long-term lifecycle support, and guaranteed industrial-temperature performance.
Supply support for 7133SA35GB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance timing, memory interface, and RF solutions, now part of Renesas Electronics.
The IDT7133/7143 family was designed specifically for deterministic dual-processor memory sharing in real-time embedded systems - emphasizing hardware arbitration, low-latency access, and robust industrial/military qualification.
FAQ
What is the function of the BUSY pin on the 7133SA35GB?
The BUSY pin on the 7133SA35GB is an open-drain output that signals port contention - i.e., when both left and right ports attempt simultaneous access to the same memory location. It stalls the lower-priority port's operation until the higher-priority access completes. External pull-up resistors are required for proper logic-level assertion. This hardware arbitration eliminates software overhead in real-time dual-CPU systems using the 7133SA35GB.
Can the 7133SA35GB operate with a 3.3 V supply?
No, the 7133SA35GB is specified exclusively for 5.0 V ±10% operation (4.5 V to 5.5 V). Its input thresholds (VIH = 2.2 V min, VIL = 0.8 V max), output drive strength, and internal logic are designed for TTL/5 V CMOS compatibility. Using 3.3 V violates absolute maximum ratings and will result in undefined behavior, failed arbitration, or data corruption. For 3.3 V systems, consider newer IDT or Renesas dual-port families explicitly rated for 3.3 V.
How does the 7133SA35GB differ from the 7143SA35GB?
The 7133SA35GB is the MASTER device with on-chip arbitration logic and open-drain BUSY outputs, while the 7143SA35GB is the SLAVE device with BUSY inputs only and no internal arbitration. The 7133SA35GB can operate stand-alone; the 7143SA35GB requires pairing with a 7133SA35GB to resolve contention. Both share identical pinouts and timing, but only the 7133SA35GB generates BUSY signals and manages priority in width-expanded memory systems.
Does the 7133SA35GB support battery backup operation?
Yes, the 7133SA35GB supports battery backup with data retention down to 2.0 V (VDR = 2.0 V), as confirmed in the datasheet's Data Retention Characteristics table. When main VCC drops below 2.0 V, the device enters data retention mode with ICCDR ≤ 4000 µA (military grade) or ≤ 1500 µA (commercial), preserving memory contents without refresh. This feature is critical for fail-safe applications like avionics and industrial controllers.
What package type is used for the 7133SA35GB?
The 7133SA35GB is supplied in a 68-pin Plastic Leaded Chip Carrier (PLCC) package, designated PLG68 in IDT documentation. Its body measures approximately 0.95 in × 0.95 in × 0.17 in, with gull-wing leads suitable for surface-mount reflow assembly. Pin 1 is marked with a notch or dot; both VCC and GND pins must be connected to ensure reliable operation per datasheet note.
7133SA35GB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-BPGA
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 68-PGA (29.46x29.46)
7133SA35GB FAQ
1.How can I place an order for 7133SA35GB through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA35GB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA35GB reliable?
The price and inventory of 7133SA35GB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA35GB is usually 5 days.
3.What payment methods are accepted for 7133SA35GB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA35GB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA35GB?
7133SA35GB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA35GB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA35GB?
For technical support, including 7133SA35GB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA35GB requirements.
6.How does Aetrix verify that 7133SA35GB is sourced from the original manufacturer or authorized distributors?
All 7133SA35GB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA35GB meets industry standards.
7.What is the process for return or replacement of 7133SA35GB?
All 7133SA35GB units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA35GB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA35GB part is unused and in its original packaging.
Return procedure for 7133SA35GB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA35GB Tags
-
M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
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AT24C02C-SSHM-T
Microchip Technology
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24LC01BT-I/OT
Microchip Technology
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M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
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AT24C04C-SSHM-T
Microchip Technology
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24LC01BT-I/SN
Microchip Technology
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24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
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