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Renesas 7133SA35JI
- Part No.:
- 7133SA35JI
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
7133SA35JI.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,709
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Product details
Overview
7133SA35JI from IDT is a high-speed 2K × 16-bit dual-port static RAM with master arbitration logic, 35 ns maximum read cycle time, TTL-compatible 5V ±10% operation, and industrial temperature range (–40°C to +85°C). It enables simultaneous asynchronous access from left and right ports in real-time embedded systems requiring deterministic memory contention resolution.
For engineers reviewing the 7133SA35JI datasheet, 7133SA35JI pinout, 7133SA35JI application, or 7133SA35JI equivalent, this page delivers verified timing parameters, BUSY arbitration behavior, byte-select write control, power-down modes, and package-specific I/O mapping for reliable integration into dual-CPU, DSP co-processor, or video frame buffer designs.
Technical Context
The 7133SA35JI implements fully asynchronous dual-port architecture with independent address, control, and bidirectional I/O buses per port. Its on-chip arbitration logic resolves port-to-port contention via open-drain BUSYL/BUSYR outputs (MASTER mode), enforcing priority-based access without external logic.
It supports separate upper/lower byte write enables (R/WLUB/R/WLLB and R/WRUB/R/WRLB), TTL-level signaling, and battery backup data retention at 2V (typical ICCDR = 100 µA). The device operates across –40°C to +85°C with VCC = 4.5–5.5V and features four standby current modes including CMOS-level full standby (ISB3 ≤ 1.0 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2K × 16 bits (32 Kbit); supports independent 16-bit reads/writes on both ports |
| Read Cycle Time (tRC) | 35 ns max - defines minimum interval between successive reads on same port |
| Address Access Time (tAA) | 35 ns max - determines latency from stable address to valid data output |
| Chip Enable Access (tACE) | 35 ns max - critical for CE-gated access timing in multi-chip systems |
| Output Enable Access (tAOE) | 20 ns max - governs data validity after OE assertion, key for burst transfers |
| Standby Current (ISB1) | 25 mA typ / 70 mA max - TTL-level standby draw when both ports disabled |
| Data Retention Voltage | 2.0 V min - enables low-power battery backup without data loss |
Pinout & Package
7133SA35JI is packaged in a 68-pin PLCC (PLG68) with 0.95″ × 0.95″ footprint. Both VCC and GND pins require connection to ensure reliable operation; unused pins are not present (no N/Cs in PLCC variant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CEL / CER | Chip Enable (Left / Right) | Active-low enable per port; controls port power state and bus drivers |
| R/WLUB / R/WRUB | Upper Byte Write Enable | Independent write control for I/O8–I/O15 on each port |
| R/WLLB / R/WRLB | Lower Byte Write Enable | Independent write control for I/O0–I/O7 on each port |
| OEL / OER | Output Enable (Left / Right) | Tri-states I/O drivers when deasserted; used for bus sharing |
| BUSYL / BUSYR | Busy Flag (Output only on 7133) | Open-drain arbitration signal indicating port contention; requires pull-up |
| A0L–A10L / A0R–A10R | Address Inputs | 11-bit address per port (2K = 2¹¹); fully asynchronous decoding |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data Bus | 16-bit parallel interface per port; high-impedance when CE or OE inactive |
Key Features
| Feature | Design Value |
|---|---|
| On-chip port arbitration logic | Resolves simultaneous access to identical addresses without external logic or software overhead |
| Separate upper/lower byte write control | Enables partial-word writes (8-bit granularity) per port, reducing bus traffic and power |
| Open-drain BUSY outputs with priority arbitration | Allows wired-OR of BUSY signals for system-level interrupt generation on contention |
| Four standby current modes | Supports dynamic power management: ISB3 ≤ 1.0 mA (CMOS full standby) minimizes idle power |
| 2V data retention capability | Preserves memory contents during main supply loss using backup battery, no refresh required |
Applications
| Real-Time Dual-CPU Systems | DSP Co-Processor Buffers |
|---|---|
Use Scenario: Two independent CPUs share memory for inter-process communication and status exchange in avionics or industrial PLCs. IC Role / Device Role / Timing Role: 7133SA35JI acts as MASTER dual-port RAM with hardware arbitration, ensuring deterministic resolution of simultaneous access to shared registers. Use Value: Eliminates software semaphores and race conditions; 35 ns tRC enables sub-30 MHz CPU handshaking without wait states. |
Use Scenario: A DSP offloads image processing while host MCU manages I/O and display; both require low-latency access to frame buffers. IC Role / Device Role / Timing Role: 7133SA35JI provides independent 16-bit data paths for concurrent read (DSP) and write (MCU) operations on overlapping memory regions. Use Value: Byte-select write enables (R/WLUB/R/WLLB) allow pixel-level updates without disturbing adjacent data; tAOE = 20 ns ensures timely pixel streaming. |
| Video Frame Synchronization | Military Radar Signal Processing |
Use Scenario: Capturing live video frames at 60 fps while simultaneously rendering overlays or performing motion analysis. IC Role / Device Role / Timing Role: 7133SA35JI serves as dual-port frame buffer - one port accepts incoming pixel data, the other feeds display controller. Use Value: Asynchronous operation prevents frame tearing; BUSY logic prevents corrupted writes during vertical blanking intervals. |
Use Scenario: Radar front-end digitizes RF returns and passes time-critical samples to signal processor under MIL-PRF-38535 QML compliance. IC Role / Device Role / Timing Role: 7133SA35JI operates as MASTER in ruggedized 7133/7143 width-expanded array (32-bit+), handling pulse-Doppler sample buffering. Use Value: Industrial temp range (–40°C to +85°C) and 35 ns timing meet airborne environmental specs; open-drain BUSY supports legacy military bus architectures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C024AV-35AXC | 32K × 16-bit, 35 ns, 3.3V core (5V tolerant I/O), no built-in arbitration logic | Requires external logic or firmware for contention resolution; higher density but larger footprint | Choose when >2K depth is needed and arbitration can be handled externally |
| IDT7143SA35JI | Same 2K × 16, 35 ns, SLAVE-only; BUSY pins are inputs (not outputs); no arbitration logic | Used only in MASTER/SLAVE width-expansion configurations; cannot operate standalone as arbitrator | Choose only as companion to 7133SA35JI in 32-bit+ bus systems |
Compared with CY7C024AV-35AXC and IDT7143SA35JI, the 7133SA35JI uniquely integrates arbitration logic and open-drain BUSY outputs - enabling true standalone dual-CPU memory sharing without added components or timing penalties.
Availability
7133SA35JI is available at Aetrix Electronics and suitable for real-time dual-CPU systems, radar signal processors, video frame synchronizers, and industrial PLCs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 7133SA35JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, and RF solutions, now part of Renesas Electronics.
The IDT7133/7143 family was designed for deterministic, low-latency memory sharing in dual-processor systems - targeting aerospace, defense, and industrial applications where hardware arbitration and MIL-PRF-38535 compliance are mandatory.
FAQ
What is the operating temperature range for the 7133SA35JI?
The 7133SA35JI is rated for industrial temperature operation from –40°C to +85°C, as confirmed in the Absolute Maximum Ratings table and supported by DC/AC electrical characteristics testing across this range. This makes it suitable for harsh-environment applications such as factory automation and outdoor communications equipment where ambient thermal stability is critical. The 7133SA35JI does not support commercial (0°C to +70°C) or military (–55°C to +125°C) grades.
Does the 7133SA35JI include on-chip arbitration logic?
Yes, the 7133SA35JI includes dedicated on-chip arbitration logic - a defining feature that distinguishes it from the SLAVE-only IDT7143 series. This logic monitors simultaneous accesses to identical addresses and asserts BUSYL or BUSYR to stall the lower-priority port. The 7133SA35JI is explicitly designated as the MASTER device in IDT's MASTER/SLAVE expansion architecture, and its BUSY pins are open-drain outputs requiring external pull-up resistors.
What package type is used for the 7133SA35JI?
The 7133SA35JI is supplied in a 68-pin plastic leaded chip carrier (PLCC), identified as PLG68 in IDT documentation. The package measures approximately 0.95 inch × 0.95 inch × 0.17 inch. It contains two VCC and two GND pins that must both be connected for reliable operation. No N/C (no-connect) pins are present in this PLCC variant - all 68 pins serve defined electrical functions.
Can the 7133SA35JI operate with a 2V backup supply?
Yes, the 7133SA35JI supports data retention at VCC = 2.0 V minimum, as specified in Table 08 (Data Retention Characteristics). In this mode, typical data retention current (ICCDR) is 100 µA, with a maximum of 4000 µA over the industrial temperature range. This allows integration into systems with coin-cell or supercapacitor backup without requiring active voltage regulation - a key requirement for fail-safe memory in power-loss scenarios.
How does byte-select write control work on the 7133SA35JI?
The 7133SA35JI provides independent upper- and lower-byte write enables: R/WLUB and R/WLLB control I/O8–I/O15 and I/O0–I/O7 on the left port, while R/WRUB and R/WRLB do the same for the right port. This allows 8-bit partial writes without affecting the complementary byte - essential for efficient register-level updates in control applications. Each pair operates asynchronously and does not require coordinated timing with CE or OE signals.
7133SA35JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 68-PLCC (24.21x24.21)
7133SA35JI FAQ
1.How can I place an order for 7133SA35JI through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA35JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA35JI reliable?
The price and inventory of 7133SA35JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA35JI is usually 5 days.
3.What payment methods are accepted for 7133SA35JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA35JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA35JI?
7133SA35JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA35JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA35JI?
For technical support, including 7133SA35JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA35JI requirements.
6.How does Aetrix verify that 7133SA35JI is sourced from the original manufacturer or authorized distributors?
All 7133SA35JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA35JI meets industry standards.
7.What is the process for return or replacement of 7133SA35JI?
All 7133SA35JI units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA35JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA35JI part is unused and in its original packaging.
Return procedure for 7133SA35JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA35JI Tags
-
M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
Microchip Technology
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AT21CS01-STUM10-T
Microchip Technology
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AT24C02C-SSHM-T
Microchip Technology
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24LC01BT-I/OT
Microchip Technology
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M24C02-FMC6TG
STMicroelectronics
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AT24CS02-SSHM-T
Microchip Technology
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93LC46BT-I/OT
Microchip Technology
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AT24C04C-SSHM-T
Microchip Technology
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24LC01BT-I/SN
Microchip Technology
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24AA02UIDT-I/OT
Microchip Technology
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AT24C08C-STUM-T
Microchip Technology
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