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Renesas 7133SA35PF
- Part No.:
- 7133SA35PF
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 100-LQFP
- Datasheet:
-
7133SA35PF.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,622
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Product details
Overview
7133SA35PF from IDT (Integrated Device Technology) is a high-speed 2K × 16-bit dual-port static RAM configured as a MASTER device with on-chip arbitration logic, BUSY output flag (open-drain), and separate upper/lower byte write controls per port. It supports 35 ns max access time at commercial/military temperature ranges, operates on single 5V ±10% supply, and enables error-free 32-bit+ bus expansion when paired with IDT7143 SLAVE devices. Used in real-time embedded systems requiring concurrent CPU/DSP memory access.
For engineers reviewing the 7133SA35PF datasheet, 7133SA35PF pinout, 7133SA35PF application, or 7133SA35PF equivalent, key selection considerations include its 68-pin PLCC package, TTL-compatible I/O, 2V data retention capability, and MASTER-specific arbitration timing (tBAA ≤ 30 ns, tBDD ≤ 35 ns).
Technical Context
The 7133SA35PF implements fully asynchronous dual-port operation with independent left/right address, control, and 16-bit bidirectional I/O buses. Its on-chip arbitration logic resolves port-to-port contention by asserting BUSYL/BUSYR outputs to stall conflicting writes - a hardware mechanism critical for deterministic real-time co-processor memory sharing.
As a MASTER device, it features open-drain BUSY outputs requiring external pull-up resistors, while SLAVE counterparts (e.g., 7143SA35PF) accept BUSY as an input to gate writes. The device supports battery backup mode (2V VCC, 100–4000 µA retention current) and offers separate R/WLUB/R/WLLB and R/WRUB/R/WRLB controls for byte-level write granularity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2K × 16-bit (32,768 bits), organized as 2048 words × 16 data lines per port |
| Access Time | 35 ns (max) - guarantees worst-case read latency for timing-critical real-time firmware |
| Supply Voltage | 5.0 V ±10% - compatible with standard TTL logic rails without level-shifting |
| Operating Temp | −55°C to +125°C (military grade) - qualified per MIL-PRF-38535 QML for harsh environments |
| Power Dissipation | 1150 mW (typ. active), 5 mW (typ. standby) - enables low-power idle states in battery-backed systems |
| Data Retention | 2 V minimum VCC - preserves memory contents during brown-out or backup battery operation |
| Package | 68-pin PLCC (PLG68) - surface-mountable, RoHS-compliant ceramic body (0.95″ × 0.95″) |
Pinout & Package
68-pin Plastic Leaded Chip Carrier (PLCC, package code PLG68) with dual-row J-lead configuration. Requires connection of both VCC and GND pins (pins 17/51 and 34/68) for reliable operation. Body dimensions: ~0.95 in × 0.95 in × 0.17 in.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L / A0R–A10R | Address Inputs (Left/Right) | 11-bit address per port selects one of 2048 memory locations independently |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data Bus (Left/Right) | 16-bit parallel data path per port; high-impedance when CE = VIH or OE = VIH |
| CEL / CER | Chip Enable (Left/Right) | Active-low enable; drives port into standby (ISB1 ≤ 80 mA) when high |
| R/WLUB / R/WRUB | Upper Byte Write Enable (Left/Right) | Controls write to I/O8–I/O15; allows byte-selective writes without disturbing lower byte |
| R/WLLB / R/WRLB | Lower Byte Write Enable (Left/Right) | Controls write to I/O0–I/O7; enables true 8-bit granularity per port |
| OEL / OER | Output Enable (Left/Right) | Tri-states I/O drivers when high; required for bus sharing in multi-device systems |
| BUSYL / BUSYR | Busy Flag (Open-Drain Output) | Indicates port contention; requires external pull-up; used to stall CPUs during arbitration |
Key Features
| Feature | Design Value |
|---|---|
| On-chip arbitration logic | Resolves simultaneous same-address access between ports without external logic, preventing data corruption |
| Separate byte write controls | Enables independent 8-bit writes to upper/lower halves of 16-bit word - essential for mixed-data-size protocols |
| MASTER/SLAVE expandability | One 7133SA35PF MASTER coordinates arbitration for multiple 7143 SLAVE devices, enabling seamless 32-bit+ bus width |
| Battery backup support | Maintains data integrity at 2V VCC with typical retention current < 4 mA - suitable for non-volatile SRAM replacement |
| TTL-compatible I/O | Direct interface with 5V microcontrollers, DSPs, and FPGAs without level translation circuitry |
Applications
| Real-Time Digital Signal Processing | Avionics Flight Control Systems |
|---|---|
Use Scenario: Dual-core DSP architecture where one core performs FFT computation while the other handles I/O buffering. IC Role / Device Role / Timing Role: MASTER 7133SA35PF serves as shared memory hub with hardware arbitration ensuring deterministic access latency. Use Value: Eliminates software mutex overhead and guarantees sub-35 ns memory access for time-critical control loops. |
Use Scenario: Redundant flight computer pair exchanging sensor fusion data and actuator commands. IC Role / Device Role / Timing Role: 7133SA35PF provides synchronized, contention-free memory access between primary and backup processors. Use Value: MIL-PRF-38535 qualification ensures reliability under vibration, thermal cycling, and radiation exposure. |
| Industrial PLC Motion Controllers | Medical Imaging Data Buffers |
Use Scenario: High-speed servo loop running at 20 kHz while background HMI updates shared status registers. IC Role / Device Role / Timing Role: 7133SA35PF acts as real-time data exchange buffer between motion engine and UI processor. Use Value: Separate byte write enables atomic updates to status flags without corrupting ongoing position data streams. |
Use Scenario: MRI subsystem transferring raw k-space data from ADC to reconstruction FPGA at >100 MB/s. IC Role / Device Role / Timing Role: Dual-port RAM buffers burst-mode ADC output while reconstruction engine reads prior frames. Use Value: 35 ns access + full asynchronous operation prevents pipeline stalls during high-throughput imaging sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Cypress CY7C1362BV33 | 3.3V core, 25 ns access, 100-pin TQFP only - no 68-pin PLCC option | Requires level-shifting for 5V systems; lacks military temp grade and BUSY arbitration logic | Choose only if migrating to 3.3V design and external arbitration is acceptable |
| IDT7143SA35PF | SLAVE-only variant: BUSY pins are inputs (not outputs); no on-chip arbitration logic | Cannot operate standalone as MASTER; must be paired with 7133SA35PF for width expansion | Select when building multi-chip 32-bit+ memory arrays where one 7133SA35PF coordinates multiple SLAVES |
Compared with CY7C1362BV33 and IDT7143SA35PF, the 7133SA35PF uniquely delivers 5V TTL compatibility, integrated arbitration, and military-grade reliability in a legacy-compatible 68-pin PLCC package - making it irreplaceable for sustaining existing high-reliability 5V dual-processor systems.
Availability
7133SA35PF is available at Aetrix Electronics and suitable for avionics, industrial motion control, and medical imaging systems requiring stable component supply, long-term obsolescence management, and traceable sourcing from authorized channels.
Supply support for 7133SA35PF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) was a fabless semiconductor company specializing in high-performance memory, timing, and interface ICs before its acquisition by Renesas Electronics in 2019. Known for robust military-qualified components and system-level timing solutions.
The IDT7133/7143 family was designed specifically for real-time embedded systems requiring deterministic, contention-free dual-processor memory access - targeting aerospace, defense, and industrial automation applications demanding guaranteed latency and fault tolerance.
FAQ
What is the function of the BUSY pins on the 7133SA35PF?
The BUSYL and BUSYR pins on the 7133SA35PF are open-drain outputs that signal port contention when both ports attempt simultaneous access to the same memory location. They require external pull-up resistors and are used to stall the contending port's write cycle. This hardware arbitration eliminates race conditions in dual-CPU or CPU-DSP architectures - a core capability distinguishing the 7133SA35PF from standard SRAMs.
Can the 7133SA35PF operate with a 3.3V supply?
No, the 7133SA35PF is specified exclusively for 5.0 V ±10% operation (4.5 V to 5.5 V). Its TTL-compatible inputs and outputs are not guaranteed to function correctly at 3.3V logic levels. Attempting 3.3V operation risks undefined behavior, excessive leakage, or failure to meet timing specifications such as the 35 ns access time. For 3.3V systems, consider modern alternatives like the Cypress CY7C1362BV33 - but note it lacks BUSY arbitration and military qualification.
How does the 7133SA35PF differ from the 7143SA35PF?
The 7133SA35PF is the MASTER device with on-chip arbitration logic and open-drain BUSY outputs, while the 7143SA35PF is the SLAVE device with BUSY inputs only and no internal arbitration. The 7133SA35PF can operate standalone; the 7143SA35PF must be paired with a 7133SA35PF to enable width expansion. Both share identical pinouts and timing, but only the 7133SA35PF generates BUSY signals and resolves contention autonomously.
Is the 7133SA35PF suitable for battery-backed applications?
Yes - the 7133SA35PF (SA version) supports data retention down to 2.0 V VCC with typical retention current of 100 µA (commercial) to 4000 µA (military). This enables use in systems with backup batteries or supercapacitors during main power loss. Retention timing parameters (tCDR, tR) are characterized per datasheet Table 8, and the device maintains data integrity without refresh cycles - unlike DRAM or some low-power SRAMs requiring periodic wake-up.
What package options are available for the 7133SA35PF?
The 7133SA35PF is available in 68-pin PLCC (PLG68), 68-pin ceramic PGA (GU68), 68-pin flatpack (FP68), and 100-pin TQFP (PNG100). The "PF" suffix in the part number specifically denotes the 68-pin PLCC package. All variants share identical electrical specifications and pin functions, but mechanical mounting, thermal performance, and board assembly requirements differ - PLCC supports reflow soldering, while PGA/flatpack are typically used in high-reliability mil-aero applications.
7133SA35PF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 100-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TQFP (14x14)
7133SA35PF FAQ
1.How can I place an order for 7133SA35PF through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA35PF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA35PF reliable?
The price and inventory of 7133SA35PF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA35PF is usually 5 days.
3.What payment methods are accepted for 7133SA35PF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA35PF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA35PF?
7133SA35PF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA35PF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA35PF?
For technical support, including 7133SA35PF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA35PF requirements.
6.How does Aetrix verify that 7133SA35PF is sourced from the original manufacturer or authorized distributors?
All 7133SA35PF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA35PF meets industry standards.
7.What is the process for return or replacement of 7133SA35PF?
All 7133SA35PF units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA35PF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA35PF part is unused and in its original packaging.
Return procedure for 7133SA35PF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA35PF Tags
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M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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AT24C02C-SSHM-T
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24LC01BT-I/OT
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M24C02-FMC6TG
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AT24CS02-SSHM-T
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93LC46BT-I/OT
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AT24C04C-SSHM-T
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24LC01BT-I/SN
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24AA02UIDT-I/OT
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AT24C08C-STUM-T
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