My Inquiry
My Account
Renesas 7133SA70JI
- Part No.:
- 7133SA70JI
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
7133SA70JI.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,455
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
7133SA70JI from IDT is a high-speed 2K × 16 dual-port static RAM with master arbitration logic, 70 ns max read cycle time, industrial temperature range (–40°C to +85°C), and TTL-compatible 5V ±10% operation - used in real-time embedded systems requiring concurrent CPU/DSP memory access without external arbitration.
For engineers reviewing the 7133SA70JI datasheet, 7133SA70JI pinout, 7133SA70JI application, or 7133SA70JI equivalent, this page delivers verified timing parameters, BUSY arbitration behavior, byte-select write control, battery backup capability (2V data retention), and package-specific pin mapping for reliable system integration.
Technical Context
The 7133SA70JI implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses. Its on-chip arbitration logic resolves port contention via open-drain BUSYL/BUSYR outputs that require pull-up resistors, enabling deterministic priority resolution without external logic.
It supports separate upper- and lower-byte write enables (R/WLUB/R/WLLB and R/WRUB/R/WRLB) per port, enabling partial writes without read-modify-write cycles. The device enters low-power standby (<1 mA typ.) when both chip enables (CEL/CER) are high, and retains data down to 2V for battery backup applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2K × 16 bits (32 Kbit), organized as 2048 words × 16-bit dual-port array |
| Access Time | 70 ns max read cycle time (tRC), supporting real-time deterministic latency in DSP co-processing |
| Operating Voltage | 5.0 V ±10% (4.5–5.5 V), TTL-compatible input thresholds and output drive levels |
| Temperature Range | Industrial grade: –40°C to +85°C, qualified per MIL-PRF-38535 QML for ruggedized systems |
| Power Consumption | Active: 230 mA typ. (ICC), Standby: 1.0 mA typ. (ISB3), enabling low-quiescent power modes |
| Data Retention | 2 V minimum VCC for data retention (VDR), supporting battery-backed SRAM operation |
| Arbitration Logic | On-chip port-to-port arbitration with BUSY flag generation - only in IDT7133-series MASTER devices |
Pinout & Package
7133SA70JI is packaged in a 68-pin PLCC (PLG68) with 0.95″ × 0.95″ footprint. Both VCC pins must be connected to 5V supply; both GND pins must be tied to ground for reliable operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CEL / CER | Chip Enable (Left / Right) | Active-low enable for respective port; controls power-down mode and bus arbitration activation |
| R/WLUB / R/WRUB | Upper Byte Write Enable (L/R) | Enables write to I/O8–I/O15; allows byte-granular writes without disturbing lower byte |
| R/WLLB / R/WRLB | Lower Byte Write Enable (L/R) | Enables write to I/O0–I/O7; supports partial-word updates in multi-processor shared memory |
| OEL / OER | Output Enable (Left / Right) | Controls tri-state of I/O drivers; independent from CE, enabling flexible bus sharing |
| BUSYL / BUSYR | Busy Flag (Output on 7133, Input on 7143) | Open-drain output on 7133SA70JI; signals port contention and gates write operations during arbitration |
| A0L–A10L / A0R–A10R | Address Inputs (L/R) | 11-bit address per port (2048 locations); fully asynchronous - no clock required |
| I/O0L–I/O15L / I/O0R–I/O15R | Data I/O (L/R) | 16-bit bidirectional data bus per port; supports simultaneous read/write across ports |
Key Features
| Feature | Design Value |
|---|---|
| Master Arbitration Logic | Integrated hardware arbitration resolves simultaneous access to same address - eliminates need for external logic or software polling |
| Byte-Selectable Write Control | Independent upper/lower byte write enables per port reduce bus traffic and avoid destructive partial writes |
| 2V Data Retention | Retains memory contents at 2V supply - enables seamless battery backup during main power loss |
| Asynchronous Dual-Port Operation | No clock required; each port operates independently with full read/write capability at any time |
| TTL-Compatible I/O | Direct interface with legacy 5V microcontrollers, DSPs, and FPGAs without level-shifting |
Applications
| Real-Time DSP Co-Processing | Redundant Controller Memory Sharing |
|---|---|
|
Use Scenario: Two DSPs share sensor data buffers and control state tables in real time with zero-latency interlock. IC Role / Device Role / Timing Role: Dual-port SRAM acts as shared memory hub; left port serves primary DSP, right port serves secondary DSP. Use Value: Eliminates software semaphore overhead and guarantees atomic access via hardware BUSY arbitration at 70 ns latency. |
Use Scenario: Primary and backup controllers maintain synchronized state in avionics or industrial safety systems. IC Role / Device Role / Timing Role: 7133SA70JI provides mirrored memory space where both controllers read/write concurrently with conflict detection. Use Value: Hardware BUSY flag triggers failover within one instruction cycle - critical for SIL-3/ISO 26262 compliance. |
| Video Frame Buffering | Military Radar Signal Processing |
|
Use Scenario: Video encoder writes frames while display controller reads previous frame - no frame tearing or dropped pixels. IC Role / Device Role / Timing Role: Left port handles pixel stream write; right port feeds parallel RGB output with precise timing alignment. Use Value: 70 ns access enables 60 fps HD video buffering with sub-microsecond inter-port synchronization. |
Use Scenario: Radar front-end FPGA captures ADC samples while DSP processes prior frame - overlapping acquisition and computation. IC Role / Device Role / Timing Role: 7133SA70JI serves as ping-pong buffer between FPGA (left port) and DSP (right port) in harsh environments. Use Value: Industrial temperature rating and MIL-PRF-38535 qualification ensure reliability under thermal shock and EMI stress. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT7143SA70JI | SLAVE-only variant; BUSY pins are inputs only (no arbitration logic); identical pinout and timing | Used only in width-expanded systems with a 7133 MASTER; cannot operate standalone as arbitrator | Select when building 32-bit+ bus systems with one 7133SA70JI MASTER and multiple SLAVE units |
| Cypress CY7C1362AV25 | 2K × 16, 25 ns access, 3.3V core (with 5V-tolerant I/O); no built-in BUSY arbitration - requires external logic | Targets modern low-voltage designs; lacks native contention resolution - increases BOM and layout complexity | Choose for 3.3V systems where external arbitration is acceptable and faster access is required |
Compared with IDT7143SA70JI and CY7C1362AV25, the 7133SA70JI uniquely integrates master arbitration logic and industrial-grade 5V operation in a single 68-pin PLCC package - reducing system-level design risk in safety-critical, real-time shared-memory applications.
Availability
7133SA70JI is available at Aetrix Electronics and suitable for real-time DSP co-processing, redundant controller memory sharing, and military radar signal processing requiring stable component supply across extended lifecycle programs.
Supply support for 7133SA70JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance memory, timing, and interface solutions for communications, computing, and industrial markets.
The IDT7133 family was designed specifically for deterministic, low-latency dual-port memory applications in real-time embedded systems - emphasizing hardware arbitration, byte-select control, and industrial/military reliability.
FAQ
What is the function of the BUSY pin on the 7133SA70JI?
The BUSY pin on the 7133SA70JI is an open-drain output that signals port contention when both left and right ports attempt simultaneous access to the same memory location. It must be pulled up externally and is used to stall the contending port's write operation. This hardware arbitration eliminates race conditions without software intervention - a core feature distinguishing the 7133SA70JI from SLAVE-only variants like the 7143SA70JI.
Does the 7133SA70JI support battery backup operation?
Yes, the 7133SA70JI supports battery backup operation with guaranteed data retention at VCC ≥ 2.0 V. In full standby mode (ISB3), it draws only 1.0 mA typical current, enabling long-term retention from a small backup cell. This capability is confirmed in the datasheet's Data Retention Characteristics table (Table 08) and applies specifically to the LA and SA versions - including the 7133SA70JI.
What package type is used for the 7133SA70JI?
The 7133SA70JI uses a 68-pin plastic leaded chip carrier (PLCC), designated PLG68 in IDT documentation. Its body measures approximately 0.95 in × 0.95 in × 0.17 in. Pin 1 is marked by a corner notch, and both VCC and GND pins must be connected to ensure reliable operation - as specified in the Pin Configurations section of the official datasheet.
Can the 7133SA70JI operate with mixed voltage interfaces?
No - the 7133SA70JI is strictly a 5V ±10% device (4.5–5.5 V) with TTL-compatible input thresholds (VIH = 2.2 V min, VIL = 0.8 V max) and output drive levels. It does not support 3.3V or mixed-voltage I/O. Interfacing with 3.3V logic requires level translation; using it outside its specified VCC range risks data corruption or permanent damage per Absolute Maximum Ratings (Table 02).
How does the 7133SA70JI differ from the 7143SA70JI?
The 7133SA70JI is the MASTER dual-port SRAM with on-chip arbitration logic and BUSY outputs, while the 7143SA70JI is the SLAVE variant with BUSY inputs only and no arbitration circuitry. They share identical pinouts, timing, and memory size, but only the 7133SA70JI can resolve contention autonomously. In width-expanded systems, one 7133SA70JI coordinates multiple 7143SA70JI units - making the 7133SA70JI indispensable for standalone arbitration functionality.
7133SA70JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 70ns
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 68-PLCC (24.21x24.21)
7133SA70JI FAQ
1.How can I place an order for 7133SA70JI through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA70JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA70JI reliable?
The price and inventory of 7133SA70JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA70JI is usually 5 days.
3.What payment methods are accepted for 7133SA70JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA70JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA70JI?
7133SA70JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA70JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA70JI?
For technical support, including 7133SA70JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA70JI requirements.
6.How does Aetrix verify that 7133SA70JI is sourced from the original manufacturer or authorized distributors?
All 7133SA70JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA70JI meets industry standards.
7.What is the process for return or replacement of 7133SA70JI?
All 7133SA70JI units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA70JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA70JI part is unused and in its original packaging.
Return procedure for 7133SA70JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA70JI Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
