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Renesas 7133SA90G
- Part No.:
- 7133SA90G
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-BPGA
- Datasheet:
-
7133SA90G.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,519
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Product details
Overview
7133SA90G from IDT is a high-speed 2K × 16 dual-port static RAM configured as a MASTER device with on-chip port arbitration logic, 90ns maximum read cycle time, TTL-compatible 5V ±10% operation, and battery backup data retention down to 2V. It enables error-free 32-bit-or-wider memory expansion when paired with IDT7143 SLAVE devices in real-time industrial control and military avionics systems.
For engineers reviewing the 7133SA90G datasheet, 7133SA90G pinout, 7133SA90G application, or 7133SA90G equivalent, key selection criteria include BUSY arbitration timing (tBDD ≤ 40ns), dual-port asynchronous access capability, 2V data retention support, and compatibility with 68-pin PLCC/PGA/flatpack or 100-pin TQFP packages for legacy board reuse.
Technical Context
The 7133SA90G implements fully asynchronous dual-port operation with independent left/right address, control, and I/O buses - enabling concurrent read/write access without internal synchronization clocks. Its on-chip arbitration logic resolves port contention by asserting open-drain BUSYL/BUSYR outputs, requiring external pull-up resistors per datasheet Note 1.
As a MASTER-only device, it supports width expansion via BUSY-driven write inhibition of SLAVE IDT7143 units; BUSY input functionality is absent - confirming exclusive MASTER role per functional block diagram and pin description tables. The device operates across military temperature range (–55°C to +125°C) with 5V ±10% supply and guarantees 90ns tRC under commercial/military conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2K × 16 bits = 4,096 words × 16-bit wide; supports independent 16-bit data paths per port. |
| Max Read Cycle Time | 90ns (military grade); defines minimum interval between successive reads on same port. |
| Supply Voltage | 5.0V ±10% (4.5V–5.5V); single-rail TTL-compatible operation with no auxiliary supplies required. |
| Data Retention | 2V minimum VCC; maintains stored data during brown-out or battery-backup mode without refresh. |
| Operating Temp | –55°C to +125°C (military grade); validated for harsh-environment deployment per MIL-PRF-38535 QML. |
| Active Power | 230mA typical ICC (both ports active at fMAX); enables thermal budgeting in dense embedded memory subsystems. |
| Standby Current | 25mA typical ISB1 (both ports disabled, TTL inputs); supports low-power sleep states in real-time systems. |
Pinout & Package
7133SA90G is available in 68-pin PLCC (PLG68), 68-pin ceramic PGA (GU68), 68-pin flatpack (FP68), and 100-pin TQFP (PNG100) packages. Pin functions are identical across all variants per datasheet Section "Description".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CEL / CER | Chip Enable (Left / Right) | Active-low enable controlling power-down state per port; CE HIGH forces standby mode (ISB1/ISB2). |
| R/WLUB / R/WRUB | Upper Byte Write Enable | Independent byte-level write control; enables selective 8-bit writes to I/O8–I/O15 on respective port. |
| R/WLLB / R/WRLB | Lower Byte Write Enable | Independent byte-level write control; enables selective 8-bit writes to I/O0–I/O7 on respective port. |
| OEL / OER | Output Enable (Left / Right) | Active-low control for tri-state output drivers; allows bus sharing without external transceivers. |
| BUSYL / BUSYR | Busy Flag (Output only) | Open-drain arbitration status signals; require external pull-up; indicate port contention to stall CPU access. |
| A0L–A10L / A0R–A10R | Address Inputs | 11-bit address per port (211 = 2048 locations); fully asynchronous with no setup/hold relative to CE/OE. |
| I/O0L–I/O15L / I/O0R–I/O15R | Data I/O Bidirectional | 16-bit parallel data path per port; high-impedance when CE or OE inactive; supports mixed read/write concurrency. |
Key Features
| Feature | Design Value |
|---|---|
| On-chip arbitration logic | Resolves simultaneous access to same memory location without external logic; eliminates race conditions in multi-CPU systems. |
| Separate byte write controls | Enables atomic 8-bit updates to upper/lower halves of 16-bit word - critical for register-mapped peripheral interfaces. |
| Open-drain BUSY outputs | Allows wired-OR of multiple 7133SA90G BUSY signals for system-level interrupt generation on contention events. |
| 2V data retention | Maintains SRAM contents during main power loss using backup battery; eliminates need for external nonvolatile storage on power fail. |
| MASTER-only configuration | Dedicated arbitration master role ensures deterministic priority resolution in width-expanded systems with IDT7143 SLAVE units. |
Applications
| Real-Time Avionics Data Buffer | Military Radar Signal Processing |
|---|---|
Use Scenario: Dual-CPU architecture where flight control processor writes sensor fusion results while display processor reads for HUD rendering. IC Role / Device Role / Timing Role: MASTER 7133SA90G arbitrates concurrent access to shared telemetry buffer; BUSY signals stall lower-priority display reads during high-integrity control writes. Use Value: Eliminates software semaphore overhead and guarantees deterministic <40ns contention resolution (tBDD), meeting DO-254 Level A timing requirements. | Use Scenario: Pulse-Doppler radar front-end with separate transmit and receive DSP engines accessing common coefficient memory. IC Role / Device Role / Timing Role: 7133SA90G serves as synchronized coefficient store; its 90ns tRC and –55°C to +125°C rating ensure stable operation in airborne environmental chambers. Use Value: Enables zero-wait-state dual-port access at 11MHz sustained bandwidth, replacing slower discrete latch+RAM solutions and reducing PCB layer count. |
| Industrial PLC I/O Mapping Memory | Secure Communications Crypto Engine |
Use Scenario: Programmable logic controller with isolated CPU and I/O processor sharing real-time status and command registers. IC Role / Device Role / Timing Role: 7133SA90G acts as deterministic inter-processor mailbox; byte-write enables atomic flag updates without corrupting adjacent status bits. Use Value: Prevents race conditions during hot-swap I/O module insertion; 2V retention preserves last-known-safe state during 100ms AC dropout events. | Use Scenario: FIPS-compliant crypto accelerator where host CPU loads keys and algorithm parameters while crypto core executes AES rounds. IC Role / Device Role / Timing Role: 7133SA90G provides tamper-resistant key storage with battery-backed retention; BUSY arbitration prevents key overwrite during active encryption. Use Value: Meets NSA Type 1 encryption module requirements for nonvolatile key persistence and concurrent access isolation without software intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C133-90JC | 90ns tRC, 2K×16, but lacks on-chip arbitration logic and BUSY signaling; requires external glue logic for contention management. | Not suitable for MASTER/SLAVE width expansion; limited to single-chip dual-port use cases without arbitration. | Select only if arbitration is handled in FPGA or if system uses single 7133SA90G without SLAVE pairing. |
| IDT7143SA90G | Pin-compatible SLAVE variant; BUSY pins are inputs (not outputs); no arbitration logic; relies on external MASTER for BUSY control. | Cannot operate standalone as arbitration master; must be used with 7133SA90G in width-expanded configurations. | Choose when building 32-bit+ memory arrays where 7133SA90G handles arbitration and IDT7143SA90G provides additional data width. |
Compared with CY7C133-90JC, 7133SA90G integrates arbitration hardware eliminating external logic and reducing BOM cost; versus IDT7143SA90G, it provides autonomous master control essential for deterministic contention resolution in safety-critical systems.
Availability
7133SA90G is available at Aetrix Electronics and suitable for real-time avionics data buffering, military radar signal processing, and industrial PLC I/O mapping requiring stable component supply across extended lifecycle programs.
Supply support for 7133SA90G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, RF, and sensor solutions for communications, computing, and industrial markets.
The IDT7133 family was designed specifically for deterministic, contention-free dual-processor memory sharing in military, aerospace, and industrial control systems demanding guaranteed arbitration and 2V data retention.
FAQ
What is the maximum operating temperature range supported by the 7133SA90G?
The 7133SA90G is rated for the military temperature range of –55°C to +125°C, compliant with MIL-PRF-38535 QML standards. This specification is confirmed in Table 2746 tbl 04 and applies to all speed grades including the 90ns version. Operation outside this range may result in undefined timing or data retention behavior, and derating is not specified in the datasheet.
Does the 7133SA90G support true dual-port concurrent read/write operations?
Yes, the 7133SA90G supports fully asynchronous concurrent access: one port can read while the other writes to any memory location. However, when both ports access the same address simultaneously, on-chip arbitration asserts BUSYL/BUSYR to stall the lower-priority port. This behavior is intrinsic to the 7133SA90G's MASTER architecture and documented in the Functional Description section.
Is the 7133SA90G pin-compatible with the IDT7143SA90G?
Yes, the 7133SA90G and IDT7143SA90G share identical pinouts across all packages (PLCC, PGA, flatpack, TQFP), as explicitly stated in the datasheet "Description" section. However, their BUSY pin functionality differs: 7133SA90G has BUSY as open-drain outputs, while IDT7143SA90G uses BUSY as inputs - requiring different external circuitry.
What is the minimum supply voltage required to retain data in the 7133SA90G?
The 7133SA90G guarantees data retention down to 2.0V VCC, as specified in Table 2746 tbl 08 under "VDR" parameter. This applies to the SA (standard power) version and enables battery backup operation during main power failure. Retention current is characterized at 100µA typical (MIL/IND) and does not require active refresh.
Can the 7133SA90G be used without external pull-up resistors on BUSY pins?
No - the BUSYL and BUSYR pins on the 7133SA90G are open-drain outputs and require external pull-up resistors to function correctly, as noted in datasheet "Functional Block Diagram" footnote 1. Omitting pull-ups will prevent BUSY signals from reaching valid HIGH levels, causing arbitration failure and potential data corruption during port contention.
7133SA90G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-BPGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 90ns
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 68-PGA (29.46x29.46)
7133SA90G FAQ
1.How can I place an order for 7133SA90G through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA90G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA90G reliable?
The price and inventory of 7133SA90G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA90G is usually 5 days.
3.What payment methods are accepted for 7133SA90G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA90G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA90G?
7133SA90G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA90G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA90G?
For technical support, including 7133SA90G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA90G requirements.
6.How does Aetrix verify that 7133SA90G is sourced from the original manufacturer or authorized distributors?
All 7133SA90G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA90G meets industry standards.
7.What is the process for return or replacement of 7133SA90G?
All 7133SA90G units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA90G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA90G part is unused and in its original packaging.
Return procedure for 7133SA90G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA90G Tags
-
M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
Microchip Technology
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AT21CS01-STUM10-T
Microchip Technology
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AT24C02C-SSHM-T
Microchip Technology
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24LC01BT-I/OT
Microchip Technology
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M24C02-FMC6TG
STMicroelectronics
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AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
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AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
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24AA02UIDT-I/OT
Microchip Technology
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AT24C08C-STUM-T
Microchip Technology
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