Renesas 7133SA90GB

Overview

7133SA90GB from IDT is a high-speed 2K × 16 dual-port static RAM configured as a MASTER device with on-chip arbitration logic, 90ns maximum read cycle time, TTL-compatible 5V ±10% operation, and open-drain BUSY output requiring external pull-up. It enables error-free 32-bit+ memory expansion when paired with IDT7143 SLAVE devices in real-time embedded systems requiring concurrent CPU/DSP access.

For engineers reviewing the 7133SA90GB datasheet, 7133SA90GB pinout, 7133SA90GB application, or 7133SA90GB equivalent, this page delivers verified timing parameters (tRC = 90ns, tAA = 90ns), dual-port arbitration behavior, battery backup capability (2V data retention), industrial-grade temperature support (–40°C to +85°C), and exact package mapping for 68-pin PLCC.

Technical Context

The 7133SA90GB implements fully asynchronous dual-port architecture with independent left/right address, control, and I/O buses - enabling simultaneous read/write operations without internal synchronization. Its on-chip arbitration logic resolves port contention by asserting BUSYL/BUSYR flags and gating write signals on the contended port.

As a MASTER device, it features open-drain BUSY outputs (BUSYL, BUSYR) with defined access/disable timing (tBAA ≤ 45ns, tBDC ≤ 30ns), supports byte-level write control (R/WLUB/R/WLLB, R/WRUB/R/WRLB), and provides full standby power-down via CE-driven logic with ISB3 ≤ 1.0mA (CMOS-level inputs).

Key Specifications

Pinout & Package

7133SA90GB is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC), with body dimensions approximately 0.95 in × 0.95 in × 0.17 in. Both VCC and GND pins must be externally connected for reliable operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with IDT7143SA90GB and CY7C133-90JC, the 7133SA90GB uniquely integrates arbitration logic and open-drain BUSY outputs - eliminating external components for contention management and enabling true plug-and-play MASTER functionality in real-time systems.

Availability

7133SA90GB is available at Aetrix Electronics and suitable for real-time DSP systems, dual-CPU communication buffers, avionics data acquisition, and industrial motion control requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature performance.

Supply support for 7133SA90GB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology) is a fabless semiconductor company specializing in high-performance timing, memory, and interface solutions, now part of Renesas Electronics.

The IDT7133/7143 family was designed specifically for deterministic, low-latency dual-processor and DSP-memory interfacing applications demanding hardware-based arbitration and seamless bus-width scalability.

FAQ

What is the function of the BUSY pins on the 7133SA90GB?

The BUSYL and BUSYR pins on the 7133SA90GB are open-drain outputs that signal port contention when both ports attempt simultaneous access to the same memory location. They require external pull-up resistors and are used to stall the contended port's write operation. This hardware arbitration eliminates race conditions without software intervention - a core feature distinguishing the 7133SA90GB as a MASTER device.

Does the 7133SA90GB support battery backup operation?

Yes, the 7133SA90GB supports battery backup operation with guaranteed data retention down to VCC = 2.0V. In this mode, current consumption drops to ≤4000µA (military grade) or ≤1500µA (commercial), allowing integration with coin-cell or supercapacitor backup circuits. The 7133SA90GB maintains all stored data without refresh during main power loss - critical for avionics and industrial black-box recorders.

Can the 7133SA90GB be used without external arbitration logic?

Yes - the 7133SA90GB contains fully integrated on-chip arbitration logic and requires no external components to resolve port contention. Its BUSY outputs directly gate write signals on the contended port. This self-contained arbitration is why the 7133SA90GB is designated a MASTER device, unlike SLAVE-only variants such as IDT7143SA90GB which rely on an external MASTER for BUSY signaling.

What package type is used for the 7133SA90GB?

The 7133SA90GB is supplied in a 68-pin Plastic Leaded Chip Carrier (PLCC) package, with mechanical dimensions of approximately 0.95 in × 0.95 in × 0.17 in. The PLCC variant is explicitly confirmed in the datasheet pin configuration diagrams and ordering information. Both VCC and GND pins must be connected to ensure reliable operation per datasheet Note 1.

How does the 7133SA90GB differ from the IDT7143SA90GB?

The 7133SA90GB is a MASTER dual-port SRAM with on-chip arbitration logic and open-drain BUSY outputs, while the IDT7143SA90GB is a SLAVE device with BUSY pins functioning solely as inputs. The 7133SA90GB can operate stand-alone or coordinate multiple SLAVE devices for 32-bit+ memory expansion; the 7143SA90GB cannot arbitrate and must be paired with a MASTER to avoid bus contention.