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Renesas 7133SA90J
- Part No.:
- 7133SA90J
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
7133SA90J.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,847
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Product details
Overview
7133SA90J from IDT is a high-speed 2K × 16 dual-port static RAM with 90 ns maximum read cycle time, TTL-compatible 5V ±10% operation, and on-chip port arbitration logic. It functions as a MASTER device with open-drain BUSY output (requiring pull-up), supports independent asynchronous access on left/right ports, and enables 32-bit+ bus expansion when paired with IDT7143 SLAVE devices - used in real-time avionics data buffers and military-grade radar memory subsystems.
For engineers reviewing the 7133SA90J datasheet, 7133SA90J pinout, 7133SA90J application, or 7133SA90J equivalent, key selection considerations include its 90 ns military-grade timing (–55°C to +125°C), dual-byte write control per port, battery backup data retention at 2V, and mandatory pull-up for BUSYL/BUSYR signals in MASTER configuration.
Technical Context
The 7133SA90J implements fully asynchronous dual-port architecture with separate address, control, and I/O buses for left and right ports. Its on-chip arbitration logic resolves contention by asserting BUSY on the losing port, with tBDD (BUSY disable to valid data) specified at 40 ns max for 90 ns speed grade.
It supports byte-level write enable (R/WLUB/R/WLLB and R/WRUB/R/WRLB), independent chip enable (CEL/CER), and output enable (OEL/OER) per port. The device enters low-power standby (<5 mW typ.) when CE is high, and retains data down to 2V for battery backup operation - a feature confirmed only for LA variants but explicitly excluded for SA series per datasheet Table 8.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2K × 16 bits (32 Kbit total, organized as two independent 2K-word ports) |
| Max Read Cycle Time | 90 ns - defines minimum interval between successive reads on same port under military temperature range |
| Supply Voltage | 5.0 V ±10% - requires both VCC pins connected; operation outside this range invalidates timing and DC specs |
| Operating Temperature | –55°C to +125°C - qualified to MIL-PRF-38535 QML for high-reliability military applications |
| Active Current (typ.) | 230 mA - measured at fMAX with both ports active, CE = VIL, outputs disabled |
| Standby Current (typ.) | 25 mA - with both CEL and CER = VIH, TTL-level inputs, f = fMAX |
| Input Capacitance | 11 pF - impacts high-frequency signal integrity and fan-out capability on address/control lines |
Pinout & Package
7133SA90J is packaged in a 68-pin PLCC (PLG68), with body dimensions approx. 0.95″ × 0.95″ × 0.17″. Both VCC and GND pins must be connected for reliable operation per datasheet Note 1–2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L / A0R–A10R | Address Inputs (Left/Right) | 11-bit address bus per port; selects one of 2K locations independently |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data Bus (Left/Right) | 16-bit parallel data path per port; high-impedance when OE or CE inactive |
| CEL / CER | Chip Enable (Left/Right) | Active-low enable; gates power-down mode - high = standby, low = active |
| R/WLUB / R/WRUB | Upper Byte Write Enable (Left/Right) | Controls write to I/O8–I/O15; allows byte-selective writes without affecting lower byte |
| R/WLLB / R/WRLB | Lower Byte Write Enable (Left/Right) | Controls write to I/O0–I/O7; enables granular 8-bit updates per port |
| OEL / OER | Output Enable (Left/Right) | Active-low; enables output drivers only when CE is also active |
| BUSYL / BUSYR | BUSY Flag (Left/Right) | Open-drain output on 7133SA (requires external pull-up); indicates port contention - asserted when both ports access same address |
Key Features
| Feature | Design Value |
|---|---|
| On-chip port arbitration logic | Resolves simultaneous access to identical addresses without external logic; ensures deterministic BUSY assertion on losing port |
| Separate upper/lower byte write control | Enables 8-bit partial writes per port - critical for protocol stack buffer management and register-mapped peripherals |
| TTL-compatible interface | Direct interfacing with legacy 5V microcontrollers and FPGAs without level-shifting circuitry |
| MIL-PRF-38535 QML qualification | Guarantees reliability, screening, and traceability for aerospace and defense deployments |
| Master-only BUSY signaling | BUSYL/BUSYR are outputs (not inputs) - distinguishes 7133SA from SLAVE 7143 and enables scalable multi-chip width expansion |
Applications
| Avionics Data Buffering | Military Radar Memory Subsystem |
|---|---|
Use Scenario: Real-time buffering of sensor fusion data between flight control processor and navigation unit in UAVs. IC Role / Device Role / Timing Role: MASTER dual-port RAM providing concurrent read/write access with hardware arbitration to prevent data corruption during burst transfers. Use Value: 90 ns military-grade timing ensures deterministic latency under thermal stress; BUSY logic eliminates need for software polling or external semaphores. |
Use Scenario: Storing digitized RF return samples in phased-array radar front-end modules operating at –40°C to +85°C. IC Role / Device Role / Timing Role: High-reliability memory node in width-expanded 64-bit memory bank using multiple 7133SA/7143SA pairs. Use Value: QML qualification guarantees radiation tolerance and long-term parametric stability; dual-byte write enables efficient sample packing into 16-bit words. |
| Secure Communication Processor Cache | Industrial Motion Controller Dual-Port Buffer |
Use Scenario: Key exchange buffer between cryptographic accelerator and host ARM core in encrypted comms module. IC Role / Device Role / Timing Role: Isolated memory partition with independent port access - prevents side-channel leakage via timing or bus contention. Use Value: Hardware arbitration enforces strict access ordering; 5V operation matches legacy crypto IC voltage domains without regulator overhead. |
Use Scenario: Synchronizing motion trajectory commands between PLC master and servo drive FPGA in CNC machinery. IC Role / Device Role / Timing Role: Deterministic inter-processor mailbox with guaranteed worst-case 90 ns response for closed-loop timing. Use Value: Asynchronous dual-port operation eliminates CPU wait states; byte-write enables atomic update of position setpoints without corrupting velocity fields. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7C133-90JC | 90 ns access, 2K × 16, but no built-in arbitration logic - requires external BUSY management | Not suitable for MASTER/SLAVE width expansion; limited to single-chip dual-port use cases | Select only if arbitration is handled in FPGA logic and board space permits external pull-ups and glue logic |
| IDT7143SA90J | Identical speed and pinout, but SLAVE-only: BUSY pins are inputs (no arbitration logic), no automatic priority resolution | Must be paired with 7133SA as MASTER; cannot operate standalone in arbitration-critical roles | Use only as companion SLAVE in 32-bit+ systems; never as drop-in replacement for 7133SA90J's MASTER functionality |
Compared with CY7C133-90JC and IDT7143SA90J, the 7133SA90J uniquely integrates on-die arbitration and MASTER BUSY output - eliminating external logic for contention resolution and enabling scalable, deterministic multi-chip memory architectures in safety-critical systems.
Availability
7133SA90J is available at Aetrix Electronics and suitable for avionics data buffering, military radar memory subsystems, and secure communication processor cache applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 7133SA90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a semiconductor company specializing in timing, memory interface, and RF solutions, now part of Renesas Electronics since 2019.
The IDT7133/7143 family was designed specifically for high-reliability dual-port memory applications demanding hardware arbitration, military temperature operation, and seamless bus-width expansion - targeting defense, aerospace, and industrial control markets.
FAQ
What is the operating temperature range for the 7133SA90J?
The 7133SA90J is rated for –55°C to +125°C and complies with MIL-PRF-38535 QML requirements. This military-grade temperature range is confirmed in datasheet Table 5 and applies specifically to the "SA" speed grade with "J" suffix. Commercial or industrial variants (e.g., 7133SA25J) have narrower ranges and are not interchangeable.
Does the 7133SA90J support battery backup data retention?
No - battery backup data retention at 2V is exclusive to the "LA" variant (e.g., 7133LA90J), as explicitly stated in datasheet Section 7 and Table 8. The 7133SA90J is a high-speed "SA" version optimized for performance, not low-voltage retention; its ISB3 full standby current is 1.0 mA (typ.), not the sub-100 µA required for battery operation.
How is BUSY functionality implemented on the 7133SA90J?
On the 7133SA90J, BUSYL and BUSYR are open-drain outputs requiring external pull-up resistors (per datasheet Note 1). They assert low during port contention to signal the losing port - a function enabled by on-chip arbitration logic unique to the MASTER 7133 device. This differs fundamentally from the SLAVE 7143, where BUSY pins are inputs only.
Can the 7133SA90J be used without external arbitration logic?
Yes - the 7133SA90J contains integrated arbitration logic and operates as a self-contained MASTER device. When two ports access the same address simultaneously, it automatically asserts BUSY on the contending port. No external semaphores, FPGA logic, or discrete arbitration circuits are needed, unlike non-arbitrating dual-port SRAMs such as the CY7C133 series.
What package type is used for the 7133SA90J?
The 7133SA90J uses a 68-pin PLCC (Plastic Leaded Chip Carrier), designated PLG68 in IDT documentation. Pin layout matches the 68-pin ceramic PGA and flatpack variants, enabling footprint compatibility across package options - though thermal and mechanical properties differ per datasheet drawings 01–02.
7133SA90J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 90ns
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 68-PLCC (24.21x24.21)
7133SA90J FAQ
1.How can I place an order for 7133SA90J through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA90J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA90J reliable?
The price and inventory of 7133SA90J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA90J is usually 5 days.
3.What payment methods are accepted for 7133SA90J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA90J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA90J?
7133SA90J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA90J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA90J?
For technical support, including 7133SA90J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA90J requirements.
6.How does Aetrix verify that 7133SA90J is sourced from the original manufacturer or authorized distributors?
All 7133SA90J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA90J meets industry standards.
7.What is the process for return or replacement of 7133SA90J?
All 7133SA90J units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA90J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA90J part is unused and in its original packaging.
Return procedure for 7133SA90J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA90J Tags
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M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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AT24C02C-SSHM-T
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24LC01BT-I/OT
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M24C02-FMC6TG
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AT24CS02-SSHM-T
Microchip Technology
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93LC46BT-I/OT
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AT24C04C-SSHM-T
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24LC01BT-I/SN
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24AA02UIDT-I/OT
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AT24C08C-STUM-T
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