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Renesas 7133SA90JI
- Part No.:
- 7133SA90JI
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
7133SA90JI.pdf
- Description:
- IC SRAM 32KBIT PARALLEL 68PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:4,525
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Product details
Overview
7133SA90JI from IDT is a high-speed 2K × 16 dual-port static RAM with master arbitration logic, 90 ns max read cycle time, TTL-compatible 5 V ±10% operation, and industrial temperature range (–40°C to +85°C). It supports independent asynchronous access on left/right ports and enables 32-bit+ bus expansion via MASTER/SLAVE configuration with IDT7143 in real-time control systems requiring deterministic contention resolution.
For engineers reviewing the 7133SA90JI datasheet, 7133SA90JI pinout, 7133SA90JI application, or 7133SA90JI equivalent, this page delivers verified timing parameters, BUSY arbitration behavior, byte-select write control, battery backup capability (2 V data retention), and package-specific layout guidance for PCB integration in avionics, motor control, and digital signal processing subsystems.
Technical Context
The 7133SA90JI implements fully asynchronous dual-port architecture with separate address, control, and I/O buses per port. Its on-chip arbitration logic resolves simultaneous accesses to identical memory locations by asserting open-drain BUSYL/BUSYR outputs-requiring external pull-up resistors-and gating writes on the contended port.
It supports byte-level write enable (R/WLUB/R/WLLB and R/WRUB/R/WRLB) and features automatic power-down via chip enable (CEL/CER), achieving 1 mW typical standby current in LA variants. The 7133SA90JI is specifically rated for 90 ns max tRC at industrial temperature, with guaranteed tAA ≤ 90 ns and tACE ≤ 90 ns under VCC = 5.0 V ±10%.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2K × 16 (32,768 bits), organized as 2048 words × 16 bits per port |
| Max Read Cycle Time (tRC) | 90 ns - defines minimum interval between successive reads on same port |
| Supply Voltage | 5.0 V ±10% - requires dual VCC pins tied to stable 4.5–5.5 V rail |
| Operating Temperature | –40°C to +85°C - qualified for industrial environments without derating |
| Standby Current (ISB3) | 0.2 mA typ. - ultra-low full-standby mode when both CE inputs > VCC − 0.2 V |
| Data Retention | 2 V minimum - retains data during brown-out or battery-backup operation |
| Input Capacitance | 11 pF - limits trace length and fanout in high-speed bus designs |
Pinout & Package
7133SA90JI is packaged in a 68-pin PLCC (PLG68) with 0.95″ × 0.95″ footprint and 0.17″ height. Both VCC and GND pins are duplicated (pins 17 & 35, pins 2 & 43) and must be connected to ensure reliable operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0L–A10L / A0R–A10R | Address Inputs (Left/Right) | 11-bit address bus per port; supports 2K-word addressing independently |
| I/O0L–I/O15L / I/O0R–I/O15R | Bidirectional Data Bus (Left/Right) | 16-bit parallel I/O per port; high-impedance when OE inactive or CE deasserted |
| CEL / CER | Chip Enable (Left/Right) | Active-low enable; controls port power-down and memory access eligibility |
| R/WLUB / R/WLLB / R/WRUB / R/WRLB | Byte Write Enable (Upper/Lower) | Independent write control for upper/lower byte of each port - enables partial-word writes |
| OEL / OER | Output Enable (Left/Right) | Active-low; gates output drivers without affecting internal memory state |
| BUSYL / BUSYR | Busy Flag (Open-Drain Output) | Indicates port contention; requires external pull-up; asserts when both ports access same address |
Key Features
| Feature | Design Value |
|---|---|
| On-chip arbitration logic | Resolves simultaneous same-address access deterministically - eliminates need for external priority encoder or glue logic |
| Master/Slave expandability | Enables 32-bit+ word width using one 7133SA90JI (MASTER) + multiple IDT7143 (SLAVE); no additional discrete logic required |
| Byte-select write control | Separate upper/lower byte write enables per port allow efficient 8-bit peripheral interfacing without masking overhead |
| Battery backup support | Retains data at VCC ≥ 2.0 V - critical for nonvolatile storage in power-loss scenarios (e.g., servo position registers) |
| TTL-compatible interface | Direct connection to 5 V microcontrollers and FPGAs without level-shifting; VIH = 2.2 V min, VIL = 0.8 V max |
Applications
| Motor Control System | Digital Signal Processor Interface |
|---|---|
Use Scenario: Real-time bidirectional data exchange between MCU and DSP in servo drive firmware, where position commands and feedback samples must be synchronized without CPU intervention. IC Role / Device Role / Timing Role: Dual-port RAM acts as shared register bank - MCU writes setpoints to left port while DSP reads them and writes status back to right port. Use Value: 90 ns tRC enables sub-microsecond inter-processor handshaking; BUSY arbitration prevents corrupted updates during concurrent access to command registers. |
Use Scenario: Co-processing architecture where FPGA handles sensor preprocessing and DSP performs FFT-based spectral analysis on streaming data. IC Role / Device Role / Timing Role: 7133SA90JI serves as ping-pong buffer - FPGA fills left port while DSP reads right port, with hardware-arbitrated address collision detection. Use Value: Independent port timing allows continuous data flow; byte-write enables selective update of coefficient tables without disturbing active filter states. |
| Avionics Flight Computer | Industrial PLC Memory Expansion |
Use Scenario: Redundant flight control unit requiring deterministic failover - primary and backup processors share state via dual-port memory with lock-free synchronization. IC Role / Device Role / Timing Role: MASTER 7133SA90JI arbitrates access; SLAVE IDT7143 expands to 32-bit word width for high-throughput telemetry logging. Use Value: MIL-PRF-38535 QML-compliant industrial grade ensures reliability at –40°C to +85°C; 2 V data retention preserves last-known safe state during power interruption. |
Use Scenario: Modular PLC backplane with hot-swappable I/O modules needing shared configuration and diagnostic data accessible by controller and HMI simultaneously. IC Role / Device Role / Timing Role: Acts as non-blocking shared memory between ARM-based controller (left port) and Cortex-M HMI processor (right port). Use Value: Asynchronous operation eliminates clock domain crossing; open-drain BUSY outputs simplify interrupt-driven conflict handling in deterministic scan cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-port SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT7143SA90JI | No on-chip arbitration logic; BUSY pins are inputs only - requires external MASTER for contention management | Suitable only as SLAVE in width-expanded systems; cannot operate standalone as dual-port memory | Select when building 32-bit+ arrays with dedicated 7133SA90JI MASTER; not interchangeable in single-chip designs |
| Cypress CY7C028V-90AC | Same 2K × 16 size and 90 ns speed, but uses 100-pin TQFP; no built-in BUSY arbitration - relies on external semaphore logic | Lacks hardware contention resolution; requires FPGA or CPLD for arbitration in multi-processor systems | Choose for space-constrained layouts where TQFP is preferred; accept added design complexity for arbitration |
Compared with IDT7143SA90JI and CY7C028V-90AC, the 7133SA90JI uniquely integrates master arbitration logic and open-drain BUSY signaling in a 68-pin PLCC, enabling standalone deterministic dual-processor communication without external logic or layout rework.
Availability
7133SA90JI is available at Aetrix Electronics and suitable for motor control systems, avionics flight computers, and industrial PLCs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 7133SA90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, and RF solutions, now part of Renesas Electronics.
The IDT7133/7143 family was designed for real-time embedded systems demanding deterministic inter-processor communication, including aerospace, industrial automation, and digital signal processing applications.
FAQ
What is the maximum operating temperature range for the 7133SA90JI?
The 7133SA90JI is rated for industrial temperature operation from –40°C to +85°C. This specification is validated per the manufacturer's test conditions and applies across all guaranteed timing parameters including 90 ns tRC, tAA, and tACE. Operation outside this range may result in timing violations or data retention failure, and is not supported by the device qualification.
Does the 7133SA90JI require external pull-up resistors on BUSY pins?
Yes, the 7133SA90JI BUSYL and BUSYR pins are open-drain outputs and require external pull-up resistors to VCC. The datasheet specifies this requirement explicitly, and omission will prevent proper assertion of the busy flag during port contention, leading to undetected write collisions and data corruption.
Can the 7133SA90JI operate with a 3.3 V supply?
No, the 7133SA90JI is specified only for 5.0 V ±10% (4.5 V to 5.5 V) operation. Its input thresholds (VIH min = 2.2 V, VIL max = 0.8 V), output drive strength, and internal logic are designed for TTL-compatible 5 V signaling. Applying 3.3 V violates the Absolute Maximum Ratings and will result in undefined behavior or functional failure.
How does the 7133SA90JI handle simultaneous access to the same memory location?
The 7133SA90JI uses on-chip arbitration logic to detect same-address access on both ports. It asserts BUSYL or BUSYR to stall the later-arriving access and gates its write signal internally. The winning port proceeds; the stalled port must wait until BUSY deasserts before retrying - ensuring deterministic, hardware-resolved contention without software intervention.
Is the 7133SA90JI pin-compatible with the IDT7143SA90JI?
Yes, the 7133SA90JI and IDT7143SA90JI share identical pinouts and package footprints (68-pin PLCC), enabling direct PCB replacement in width-expanded systems. However, their BUSY pin functionality differs fundamentally: 7133SA90JI drives BUSY as an output, while IDT7143SA90JI receives BUSY as an input - requiring corresponding schematic changes for correct signal routing.
7133SA90JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 68-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Dual Port, Asynchronous
- Memory Size:
- 32Kbit
- Memory Organization:
- 2K x 16
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 90ns
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 68-PLCC (24.21x24.21)
7133SA90JI FAQ
1.How can I place an order for 7133SA90JI through Aetrix?
Please submit a Request for Quotation (RFQ) for 7133SA90JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 7133SA90JI reliable?
The price and inventory of 7133SA90JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 7133SA90JI is usually 5 days.
3.What payment methods are accepted for 7133SA90JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 7133SA90JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 7133SA90JI?
7133SA90JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 7133SA90JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 7133SA90JI?
For technical support, including 7133SA90JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 7133SA90JI requirements.
6.How does Aetrix verify that 7133SA90JI is sourced from the original manufacturer or authorized distributors?
All 7133SA90JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 7133SA90JI meets industry standards.
7.What is the process for return or replacement of 7133SA90JI?
All 7133SA90JI units undergo pre-shipment inspection (PSI). If there is an issue with 7133SA90JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 7133SA90JI part is unused and in its original packaging.
Return procedure for 7133SA90JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
7133SA90JI Tags
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