Renesas 728985JG
- Part No.:
- 728985JG
- Manufacturer:
- Renesas
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
728985JG.pdf
- Description:
- IC MULTIPLEXER 1 X 8:8 44PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:3,175
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Product details
Overview
IDT728985JG from Integrated Device Technology is a 256 × 256 non-blocking time slot interchange (TSI) digital switch IC for ST-BUS®/GCI telecommunication backplanes, supporting 8 RX and 8 TX serial streams at 2.048 Mb/s, 5 V supply, and −40°C to +85°C operation in PLCC-44 package.
For engineers reviewing the IDT728985JG datasheet, IDT728985JG pinout, IDT728985JG application, or IDT728985JG equivalent, key selection considerations include per-channel variable/constant throughput delay mode selection, microprocessor-controlled connection memory access (A0–A5, D0–D7, CS/DS/R/W), frame integrity support for PCM/data networks, and ST-BUS®/GCI auto-detection via F0i/C4i inputs.
Technical Context
The IDT728985JG implements a dual-mode TSI architecture with independent Connection Memory High (CMH) and Connection Memory Low (CML) for per-channel switching control. It supports both Connection Mode (data routed from Data Memory based on CML addresses) and Processor Mode (data written directly to CML by host CPU).
Its timing unit automatically detects ST-BUS® (active-low frame sync) or GCI (active-high frame sync) formats using F0i and C4i inputs, then configures internal sampling edges accordingly. Variable Delay mode achieves minimum 3-slot latency; Constant Delay mode guarantees frame-aligned 32–94 slot delays using multi-buffered Data Memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Capacity | 256 × 256 non-blocking time slot interchange - enables full-mesh TDM channel routing across 8 input and 8 output serial streams. |
| Data Rate per Stream | 2.048 Mb/s - matches E1/T1 framing standards; each stream carries 32 × 64 kbit/s PCM channels. |
| Supply Voltage | +5.0 V (4.75–5.25 V) - compatible with legacy 5 V telecom logic families and eliminates level-shifting requirements. |
| Operating Temperature | −40°C to +85°C - qualified for industrial and extended commercial base station and network equipment environments. |
| Microprocessor Interface | 8-bit non-multiplexed bus (D0–D7, A0–A5, CS, DS, R/W, DTA) - allows direct attachment to 8051, Z80, or similar controllers without glue logic. |
| Delay Modes | Per-channel selectable Variable (3–34 slots) or Constant (32–94 slots) throughput delay - preserves voice latency or data frame integrity as required. |
| Frame Sync Detection | Auto-identifies ST-BUS® (F0i active-low) or GCI (F0i active-high) format - eliminates manual configuration and supports mixed-backplane systems. |
Pinout & Package
Package: 44-pin Plastic Leaded Chip Carrier (PLCC, J44-1), 0.05 in pitch, 0.65 in × 0.65 in footprint, lead-free (Green) variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND | Ground reference | Primary ground rail for analog and digital sections; requires low-impedance PCB plane connection. |
| VCC | Power supply | +5.0 V supply input; decoupling capacitor (0.1 µF) required adjacent to pin. |
| RX0–RX7 | Serial input streams | 8 unidirectional TDM inputs; each accepts 32-channel 2.048 Mb/s PCM data with automatic frame alignment. |
| TX0–TX7 | Serial output streams | 8 three-state TDM outputs; individually controllable via CMH bit 0 and global ODE pin. |
| F0i | Frame synchronization input | Accepts 8 kHz frame pulse; auto-detects polarity for ST-BUS®/GCI compatibility. |
| C4i | Serial clock input | 4.096 MHz master clock; defines bit timing and sampling edges per detected interface standard. |
| A0–A5 | Address bus | 6-bit address for accessing Control Register, Connection Memory (High/Low), or Data Memory locations. |
| D0–D7 | Data bus | 8-bit bidirectional interface for read/write of internal memories and registers; supports non-multiplexed MPU timing. |
| CS, DS, R/W | Control strobes | Chip Select, Data Strobe, and Read/Write enable signals - implement standard Motorola-style parallel bus protocol. |
| DTA | Data Acknowledge | Open-drain active-low signal indicating completion of bus transfer; requires external pull-up resistor. |
| ODE | Output Drive Enable | Global three-state control for all TX outputs; overrides per-channel OE bits when asserted low. |
| CCO | Control Channel Output | 2.048 Mb/s serial output carrying 256 programmable bits (one per time slot), synchronized to TX streams. |
Key Features
| Feature | Design Value |
|---|---|
| ST-BUS®/GCI Auto-Detection | Eliminates manual interface configuration by sensing F0i polarity and adapting internal timing edges to match specification. |
| Per-Channel Delay Mode Selection | Enables mixed-traffic systems: voice paths use Variable Delay (minimizing latency), data paths use Constant Delay (preserving frame alignment). |
| Split Memory Access Mode | Allows simultaneous CPU reads from Data Memory and writes to Connection Memory Low - simplifies real-time reconfiguration without bus contention. |
| Programmable Output Drivers | Combines global ODE pin with per-channel OE bits in CMH to support flexible bus-sharing topologies and hot-swap-safe designs. |
| Frame Integrity Guarantee | In Constant Delay mode, all switched data maintains exact inter-channel timing relationships across frames - critical for ISDN, ATM adaptation, and packetized voice. |
Applications
| ISDN Primary Rate Interface (PRI) | TDM Multiplexer/Demultiplexer |
|---|---|
Use Scenario: Aggregating 30 B-channels and 1 D-channel from multiple E1 lines into a centralized switching fabric. IC Role / Device Role / Timing Role: Time slot interchange switch performing dynamic cross-connection between incoming and outgoing E1 streams under MPU control. Use Value: Enables flexible call routing and trunk group management while maintaining strict 125 µs frame boundaries and sub-100 ns jitter accumulation. |
Use Scenario: Consolidating 8 × 2.048 Mb/s E1 feeds into a single high-speed backplane interface for core router or media gateway. IC Role / Device Role / Timing Role: Digital switch providing lossless time-division multiplexing with per-channel source selection and delay control. Use Value: Reduces physical layer complexity by replacing discrete mux/demux logic with a single configurable IC supporting both broadcast and point-to-point channel mapping. |
| VoIP Gateway Media Processing | Legacy PBX Digital Trunk Interface |
Use Scenario: Bridging TDM voice channels from analog/digital line cards to packet-based VoIP processing engines. IC Role / Device Role / Timing Role: TSI device buffering and aligning PCM samples prior to packetization, with variable delay mode minimizing end-to-end talker echo. Use Value: Achieves <3 ms total processing latency (including IDT728985JG's 3-slot min delay) while preserving channel synchronization for wideband codec support. |
Use Scenario: Interfacing modern control processors with legacy digital trunk modules requiring ST-BUS®-compliant signaling. IC Role / Device Role / Timing Role: Protocol-transparent time slot router enabling software-defined trunk assignment and maintenance channel insertion. Use Value: Extends service life of installed PBX hardware by decoupling control logic from physical layer timing - no FPGA or ASIC redesign needed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar time slot interchange applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| RENESAS IDT72V2115L15PF | 32 × 32 capacity, 3.3 V core, LVCMOS I/O; lacks ST-BUS®/GCI auto-detect and frame integrity modes. | Suitable only for low-density, low-power embedded TSI where constant delay and backplane format flexibility are not required. | Select when system operates at 3.3 V and needs smaller footprint; not drop-in for IDT728985JG's 256×256 scale or 5 V environment. |
| ON Semiconductor NB7L14M | 8×8 digital crosspoint switch, 3.3 V, 4 Gbps serial rate; no TSI functionality, memory, or frame-aware timing. | Designed for high-speed SerDes routing, not TDM time-slot manipulation; no support for PCM framing or delay modes. | Choose only for non-TDM, packet-switched interconnect; cannot replace IDT728985JG in voice/data circuit-switched applications. |
Compared with IDT728985JG, the IDT72V2115L15PF offers lower power and voltage but sacrifices scalability and telecom-specific features, while the NB7L14M provides raw bandwidth without time-slot awareness - neither supports the IDT728985JG's frame-aligned 256×256 switching, auto-format detection, or guaranteed minimum/maximum delay guarantees essential for E1 infrastructure.
Availability
IDT728985JG is available at Aetrix Electronics and suitable for ISDN PRI gateways, TDM multiplexers, VoIP media gateways, and legacy PBX digital trunk interfaces requiring stable component supply across long-lifecycle telecom deployments.
Supply support for IDT728985JG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Integrated Device Technology (IDT), now part of Renesas Electronics, is a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions for communications and computing markets.
IDT728985JG belongs to IDT's Time Slot Interchange product line, designed specifically for carrier-grade TDM switching in E1/T1 infrastructure, supporting ST-BUS® and GCI protocols with deterministic latency and frame integrity.
FAQ
What is the primary function of the IDT728985JG in a telecommunications system?
The IDT728985JG serves as a 256 × 256 time slot interchange digital switch that dynamically routes individual 64 kbit/s PCM time slots between eight input (RX0–RX7) and eight output (TX0–TX7) serial streams. It enables non-blocking circuit-switched connections in E1/T1 infrastructure, supporting both Connection Mode (hardware-directed routing) and Processor Mode (CPU-programmed data injection), making it essential for ISDN PRI gateways, TDM multiplexers, and digital trunk interfaces where precise time-slot manipulation is required.
Does the IDT728985JG support both ST-BUS® and GCI interface standards?
Yes, the IDT728985JG incorporates automatic interface detection via its F0i frame sync input and C4i clock input. It senses whether the incoming frame pulse is active-high (GCI) or active-low (ST-BUS®) and internally configures its serial timing unit accordingly - including bit sampling edges and frame boundary alignment - eliminating the need for external configuration or mode pins. This dual-standard support is confirmed in the functional description and timing diagrams (Figures 7 and 8) of the official datasheet.
What are the two throughput delay modes supported by the IDT728985JG, and how do they differ?
The IDT728985JG supports Variable Delay mode (minimum 3 time slots, up to 34 slots) and Constant Delay mode (32–94 time slots). In Variable Delay mode, latency depends solely on input–output time slot offset, optimizing for voice where low latency is critical. In Constant Delay mode, all switched data maintains fixed frame alignment - input frame N always appears on output frame N+2 - ensuring inter-channel timing integrity for data services like ISDN B-channel bonding or ATM cell assembly. Both modes are selectable per channel via bit 6 (V/C) in Connection Memory High.
How does the microprocessor interface of the IDT728985JG operate, and what signals are required?
The IDT728985JG uses a non-multiplexed 8-bit parallel interface with six address lines (A0–A5), eight data lines (D0–D7), and four control signals: CS (chip select, active-low), DS (data strobe, active-high), R/W (read/write direction), and DTA (data acknowledge, open-drain active-low). This Motorola-compatible bus allows direct connection to 8051, Z80, or similar microcontrollers. The DTA signal indicates transfer completion, with acknowledgment delays ranging from 40 ns (control register) to 1220 ns (Data Memory reads), as specified in the timing tables.
What package type is used for the IDT728985JG, and is it RoHS-compliant?
The IDT728985JG is packaged in a 44-pin Plastic Leaded Chip Carrier (PLCC, order code J) with 0.05 inch pitch and 0.65 inch × 0.65 inch body size (J44-1). Per the ordering information on page 13 of the datasheet, the "JG" suffix denotes the green (lead-free/RoHS-compliant) version. This is confirmed by the package documentation reference PSC4008.pdf and the explicit labeling "Green Plastic Leaded Chip Carrier" in the part number decoding table.
728985JG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- 7200
- Package/Case:
- 44-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Multiplexer
- Circuit:
- 1 x 8:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
728985JG FAQ
1.How can I place an order for 728985JG through Aetrix?
Please submit a Request for Quotation (RFQ) for 728985JG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 728985JG reliable?
The price and inventory of 728985JG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 728985JG is usually 5 days.
3.What payment methods are accepted for 728985JG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 728985JG transactions.
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4.How is shipping managed for 728985JG?
728985JG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 728985JG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 728985JG?
For technical support, including 728985JG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 728985JG requirements.
6.How does Aetrix verify that 728985JG is sourced from the original manufacturer or authorized distributors?
All 728985JG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 728985JG meets industry standards.
7.What is the process for return or replacement of 728985JG?
All 728985JG units undergo pre-shipment inspection (PSI). If there is an issue with 728985JG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 728985JG part is unused and in its original packaging.
Return procedure for 728985JG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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