Renesas 72V73273BB

Overview

72V73273BB from Integrated Device Technology (IDT) is a 3.3 V, 208-pin PBGA time slot interchange (TSI) digital switch engineered for TDM-based voice and data multiplexing. It delivers non-blocking 32,768 × 32,768 channel switching at up to 32.768 Mb/s, supports 64 serial RX/TX streams, and operates across −40°C to +85°C for industrial telecom infrastructure.

For engineers reviewing the 72V73273BB datasheet, 72V73273BB pinout, 72V73273BB application, or 72V73273BB equivalent, this device serves as a high-density, rate-matching TSI core in ST-BUS®/GCI-compliant systems requiring per-channel delay control, JTAG testability, and microprocessor-accessible connection memory.

Technical Context

The 72V73273BB implements dual-path memory architecture: Data Memory stores incoming RX stream data synchronized to the 8 kHz F32i frame pulse, while Connection Memory (split into HIGH/LOW) defines per-channel routing, mode (Variable/Constant Delay, Processor, BERT), and output enable state. Its 32.768 MHz C32i master clock enables bit-accurate sampling across five data rates (2.048–32.768 Mb/s) without external rate-specific clocks.

Switching logic supports two primary operational modes: Connection Mode uses Connection Memory to map RX channels to TX outputs with frame-aligned latency; Processor Mode allows real-time microprocessor writes to Connection Memory LOW for dynamic per-channel payload injection. Frame Offset programming (±7.5 clock cycles) compensates for inter-stream skew, and RX/TX internal bypass reduces I/O delay to nanoseconds.

Key Specifications

Pinout & Package

208-pin Plastic Ball Grid Array (PBGA), 17 mm × 17 mm, 1 mm pitch (order code BB). Package complies with JEDEC MO-251 and supports standard reflow profiles for high-reliability telecom PCB assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V73272BB and PMC-Sierra PM73273, the 72V73273BB offers maximum channel density in IDT's footprint-compatible family and direct drop-in replacement for prior IDT72V73xxx designs, whereas alternatives require either capacity trade-offs or full firmware requalification.

Availability

72V73273BB is available at Aetrix Electronics and suitable for voice over E1/T1 access gateways, multi-service aggregation routers, SONET/SDH add-drop multiplexers, and industrial TDM backplane controllers requiring stable component supply across extended product lifecycles.

Supply support for 72V73273BB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and TDM switching solutions before its acquisition by Renesas Electronics in 2019. IDT pioneered high-density TSI architectures for telecom infrastructure.

The 72V73273BB belongs to IDT's 72V73xxx family of time slot interchange switches, designed specifically for carrier-class TDM cross-connect applications demanding non-blocking switching, multi-rate support, and industrial temperature reliability.

FAQ

What is the maximum data rate supported by the 72V73273BB?

The 72V73273BB supports a maximum data rate of 32.768 Mb/s per serial stream, corresponding to 512 channels per 125 µs frame. This rate is enabled by its 32.768 MHz C32i master clock, which provides one clock edge per bit at full speed. Lower rates (2.048–16.384 Mb/s) are achieved using clock division within the device, with no external clock required.

How does the 72V73273BB handle frame synchronization across mixed-rate streams?

The 72V73273BB uses the F32i input to detect 8 kHz frame boundaries and automatically identifies ST-BUS® or GCI protocol polarity. Per-stream frame delay offset programming (±7.5 clock cycles in half-cycle steps) compensates for skew between asynchronous input sources, ensuring aligned switching across all 64 RX streams regardless of origin or rate.

Can the 72V73273BB operate in both Variable and Constant Delay Modes simultaneously?

Yes - the 72V73273BB supports per-channel delay mode selection via MOD2-0 bits in Connection Memory HIGH. One channel can be configured for Variable Delay (MOD2-0 = 000) to minimize voice latency, while another uses Constant Delay (MOD2-0 = 001) to preserve frame integrity for data payloads, all within the same device instance.

What is the purpose of the ODE and OSB pins on the 72V73273BB?

The ODE (Output Drive Enable) pin is a hardware-level global control that places all TX outputs in High-Z when asserted low, used during power-up initialization. The OSB (Output Standby) bit in the Control Register provides software-controlled equivalent functionality. Both must be low for full output disable; either high enables driver operation, subject to per-channel MOD2-0 settings.

Does the 72V73273BB support JTAG boundary-scan testing?

Yes - the 72V73273BB includes a fully compliant IEEE-1149.1 JTAG Test Access Port with dedicated TCK, TMS, TDI, TDO, and TRST pins. This enables structural testing, in-system programming verification, and runtime diagnostics without disrupting normal TSI operation or requiring external test fixtures.