Renesas 72V90823PF

Overview

IDT72V90823PF from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch optimized for ST-BUS®/GCI and wide frame pulse (WFP) telecommunication interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable or constant throughput delay, IEEE-1149.1 JTAG test port, and 5V-tolerant I/O - deployed in carrier-grade TDM switching systems requiring precise channel-level timing control.

For engineers reviewing the IDT72V90823PF datasheet, IDT72V90823PF pinout, IDT72V90823PF application, or IDT72V90823PF equivalent, key selection considerations include frame alignment mode (ST-BUS®/GCI vs. WFP), microprocessor interface configuration (multiplexed/non-multiplexed), per-channel high-impedance output control via ODE and connection memory, input frame offset calibration, and CCO bit-synchronous control output timing.

Technical Context

The IDT72V90823PF implements a dual-mode serial interface: ST-BUS®/GCI auto-detection when WFPS = LOW (using F0i and FE/HCLK), and fixed 4.096 MHz HCLK-aligned WFP mode when WFPS = HIGH. Its internal architecture includes 16 RX/TX serial streams, parallel microprocessor port (AD0–AD7/D8–D15/A0–A7), and dedicated frame evaluation logic for skew measurement across backplane paths.

Switching operation relies on 8 KHz frame-aligned connection memory (2,048 locations) with five per-channel control bits - enabling Processor Mode (direct TX data write), Connection Mode (source address mapping), V/C delay selection, loopback, and CCO bit output. Throughput delay is programmable per channel: minimum 3 time-slots (variable mode) or fixed 1-frame latency (constant mode).

Key Specifications

Pinout & Package

Package: 100-pin Thin Quad Flatpack (TQFP), 0.50 mm pitch, 14 mm × 14 mm footprint (order code PF). Pin 1 marked by index corner; IC pin tied to GND for normal IEEE 1149.1 compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V90822PF and CY7C9252AV-10JXC, the IDT72V90823PF uniquely supports 8.192 Mb/s operation with full 2,048 × 2,048 switching, WFP frame alignment, and IEEE-1149.1 test infrastructure - making it the sole option for carrier-class multi-E1 aggregation with production test coverage and backplane skew resilience.

Availability

IDT72V90823PF is available at Aetrix Electronics and suitable for telecom access multiplexers, digital loop carrier systems, VoIP gateways, and multi-service provisioning platforms requiring stable component supply across extended product lifecycles.

Supply support for IDT72V90823PF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions before its acquisition by Renesas Electronics in 2019. IDT72V90823PF reflects its legacy leadership in TDM switching silicon.

IDT72V90823PF belongs to IDT's time slot interchange (TSI) digital switch product line, designed specifically for carrier-grade telecommunication infrastructure requiring deterministic low-latency channel switching, frame-aligned synchronization, and multi-standard interface flexibility (ST-BUS®, GCI, WFP).

FAQ

What is the maximum serial data rate supported by the IDT72V90823PF?

The IDT72V90823PF supports a maximum serial data rate of 8.192 Mb/s, achieved when DR0=0 and DR1=1 in the IMS register. At this rate, the device operates with 16 RX/TX streams, each carrying 128 × 64 kbit/s channels per 125 µs frame, and requires a 16.384 MHz master clock (CLK) input. Lower rates of 4.096 Mb/s and 2.048 Mb/s are also supported with corresponding scaling of channel count and clock frequency.

How does the IDT72V90823PF handle frame synchronization for ST-BUS® and GCI interfaces?

The IDT72V90823PF automatically detects and configures for ST-BUS® or GCI frame formats when the WFPS pin is LOW. It identifies frame polarity by analyzing the F0i input and aligns serial data sampling accordingly: rising-edge sampling at three-quarters of the bit cell for GCI, falling-edge sampling for ST-BUS®. This hardware-level detection eliminates software initialization complexity and ensures robust lock under varying signal conditions.

Can the IDT72V90823PF perform per-channel high-impedance control on its TX outputs?

Yes, the IDT72V90823PF supports per-channel high-impedance control via the OE bit in each location of its connection memory. When enabled, this bit places the corresponding TX output (e.g., TX3, channel 12) into high-Z state independently of other channels. Additionally, global control is available through the ODE pin and OSB bit in the IMS register, which override per-channel settings when asserted.

What is the purpose of the CCO pin on the IDT72V90823PF?

The CCO (Connection Control Output) pin on the IDT72V90823PF outputs the CCO bit from each connection memory location sequentially, synchronized to the active serial data rate - delivering 512, 1,024, or 2,048 bits per frame at 4.096, 8.192, or 16.384 Mb/s respectively. It is timed one time-slot ahead of the associated TX channel and is used to drive external control logic such as channel-specific gain adjustment or dynamic resource allocation in hybrid TDM/IP systems.

Does the IDT72V90823PF support JTAG boundary scan testing?

Yes, the IDT72V90823PF fully complies with IEEE-1149.1 (JTAG) standards via dedicated pins TMS, TDI, TDO, TCK, and TRST. The JTAG interface enables boundary scan testing, in-circuit debugging, and device identification during manufacturing and field maintenance. The IC pin must be tied to GND for proper JTAG operation and IEEE 1149.1 compliance.