Renesas 72V90823PF8

Overview

IDT72V90823PF8 from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch optimized for ST-BUS®/GCI and wide frame pulse (WFP) telecommunication interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable/constant throughput delay, IEEE-1149.1 JTAG test port, and 5V-tolerant I/O - deployed in carrier-grade TDM switching systems requiring precise channel-level timing control.

For engineers reviewing the IDT72V90823PF8 datasheet, IDT72V90823PF8 pinout, IDT72V90823PF8 application, or IDT72V90823PF8 equivalent, key selection considerations include frame alignment evaluation capability (FE/HCLK), per-channel high-impedance output control (ODE + OSB bit), microprocessor interface mode flexibility (IM pin), input frame offset calibration (FOR registers), and WFP vs. ST-BUS®/GCI mode selection (WFPS pin).

Technical Context

The IDT72V90823PF8 implements a dual-mode serial interface: ST-BUS®/GCI auto-detection (via F0i polarity sensing) and WFP alignment (with FE/HCLK at 4.096 MHz and CLK at 16.384 MHz). Its internal architecture includes 8 KHz frame-synchronized data memory, connection memory with per-channel control bits (V/C, LPBK, PC, OE), and parallel-to-serial converters supporting 16 RX/TX streams.

Switching operation is governed by IMS register configuration (DR0–DR1 for data rate, SFE for frame evaluation, OSB for global output standby) and connection memory mapping (CAB/SAB for source addressing). Throughput delay is programmable per channel: variable mode achieves minimum 3-time-slot latency; constant mode guarantees fixed 1-frame delay with full frame integrity for concatenated data.

Key Specifications

Pinout & Package

Package: 100-pin Thin Quad Flatpack (TQFP), 0.50 mm pitch, 14 mm × 14 mm footprint (order code PF). Pinout validated per IDT DSC-5712/4 datasheet Figure 5 (TQFP top view) and Pin Description Table (pages 4–5).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with MC145508P and Si2404-GM, the IDT72V90823PF8 delivers unmatched scalability (2K×2K), dual-mode frame alignment (ST-BUS®/WFP), and per-channel programmability - making it the only option supporting both carrier-grade TDM switching and adaptive mixed-rate backplane integration.

Availability

IDT72V90823PF8 is available at Aetrix Electronics and suitable for central office switching, VoIP gateway TDM bridging, wireless base station Abis aggregation, and secure communications multiplexing requiring stable component supply across extended product lifecycles.

Supply support for IDT72V90823PF8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions before its acquisition by Renesas Electronics in 2019.

The IDT72V90823PF8 belongs to IDT's legacy TSI digital switch family, engineered specifically for carrier-class TDM infrastructure requiring deterministic latency, multi-standard frame alignment, and scalable non-blocking channel density.

FAQ

What is the maximum serial data rate supported by the IDT72V90823PF8?

The IDT72V90823PF8 supports a maximum serial data rate of 8.192 Mb/s, enabling 2,048 × 2,048 non-blocking channel switching. At this rate, the device requires a 16.384 MHz master clock (CLK) and operates with 128 time-slots per 125 μs frame. Lower rates - 4.096 Mb/s (1,024 × 1,024) and 2.048 Mb/s (512 × 512) - are also fully supported with corresponding clock and frame configurations.

How does the IDT72V90823PF8 handle frame synchronization for ST-BUS® versus GCI interfaces?

The IDT72V90823PF8 automatically detects ST-BUS® or GCI frame format based on the polarity and edge timing of the F0i input signal. In ST-BUS® mode, bit boundaries align with every second falling edge of CLK; in GCI mode, they align with every second rising edge. This auto-detection occurs without software intervention and is confirmed in the functional description section of the IDT72V90823PF8 datasheet.

Can the IDT72V90823PF8 operate in both variable and constant throughput delay modes simultaneously?

Yes - the IDT72V90823PF8 supports per-channel selection of variable or constant throughput delay via the V/C bit in each location of its connection memory. One channel may use variable delay (minimizing voice latency), while another uses constant delay (preserving frame integrity for data), all within the same device instance and frame cycle.

What is the purpose of the IC pin on the IDT72V90823PF8, and how must it be connected?

The IC pin on the IDT72V90823PF8 is an internal connection pin that must be tied to GND for normal operation and IEEE-1149.1 JTAG compliance. Leaving IC floating or connecting it to VCC will prevent proper JTAG boundary scan functionality and may cause undefined behavior during reset or configuration sequences.

Does the IDT72V90823PF8 require external pull-up resistors on any pins, and if so, which ones?

Yes - the IDT72V90823PF8 requires an external pull-up resistor on the DTA (Data Transfer Acknowledgment) pin to maintain a HIGH level when the pin enters high-impedance state after bus cycle completion. The datasheet specifies this is necessary to enable faster bus cycles with weaker drive strength; no other pins mandate external pull-ups beyond standard JTAG (TMS, TDI, TRST) best practices.