Renesas 72V90823PFG

Overview

IDT72V90823PFG from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch optimized for ST-BUS®/GCI and wide frame pulse (WFP) telecommunication interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s across 16 RX/TX streams, delivers per-channel variable or constant throughput delay, and integrates IEEE-1149.1 JTAG test capability. It is used in carrier-grade TDM switching systems requiring precise channel-level timing control and frame integrity.

For engineers reviewing the IDT72V90823PFG datasheet, IDT72V90823PFG pinout, IDT72V90823PFG application, or IDT72V90823PFG equivalent, key selection criteria include confirmed 84-pin PLCC package mapping, verified 5V-tolerant I/O compatibility with Intel/Motorola microprocessor buses, validated per-stream frame offset calibration, and documented support for both ST-BUS®/GCI auto-detection and WFP alignment modes.

Technical Context

The IDT72V90823PFG implements a dual-mode serial interface: in ST-BUS®/GCI mode, it auto-detects frame polarity and aligns to either format using F0i and FE/HCLK; in WFP mode (WFPS = HIGH), it uses HCLK at 4.096 MHz and CLK at 16.384 MHz for deterministic frame alignment. Its internal architecture includes separate serial-to-parallel and parallel-to-serial converters per stream, a 2,048-location connection memory with per-channel control bits (V/C, LPBK, PC, OSB), and dedicated frame input offset registers (FOR) for skew compensation up to +4.5 CLK periods.

Switching operation occurs in two distinct modes: Connection Mode uses source address bits (SAB/CAB) to route data from data memory to TX outputs; Processor Mode writes direct payload data into connection memory for immediate per-channel output. Delay behavior is programmable per channel - variable delay achieves minimum latency (as low as 3 time-slots), while constant delay guarantees fixed one-frame throughput for frame-aligned data applications.

Key Specifications

Pinout & Package

Package: 84-pin Plastic Leaded Chip Carrier (PLCC), 0.05-inch pitch, 1.15-inch × 1.15-inch footprint (order code: J). All I/O pins except TMS, TDI, TRST are 5V tolerant; IC pin must be tied to GND for normal operation and IEEE-1149.1 compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V90825PFG, the IDT72V90823PFG offers identical feature set at lower channel count and reduced memory footprint - ideal for mid-scale access nodes. Versus CY7C4265V-10JXC, it provides superior interoperability across mixed-format networks and built-in testability, at the cost of higher pin count and complexity.

Availability

IDT72V90823PFG is available at Aetrix Electronics and suitable for telecom access multiplexers, digital loop carrier systems, carrier-grade VoIP gateways, and TDM-over-IP edge routers requiring stable component supply across extended product lifecycles.

Supply support for IDT72V90823PFG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions before its acquisition by Renesas Electronics in 2019.

The IDT72V90823PFG belongs to IDT's TSI digital switch family, designed specifically for carrier-class TDM infrastructure requiring deterministic channel switching, multi-format frame alignment, and robust microprocessor integration in space-constrained PLCC packages.

FAQ

What is the maximum serial data rate supported by the IDT72V90823PFG?

The IDT72V90823PFG supports a maximum serial data rate of 8.192 Mb/s, achieved when configured for 2,048 × 2,048 channel switching. At this rate, it operates with 128 time-slots per 125 µs frame and requires a 16.384 MHz master clock (CLK) input. Lower rates of 4.096 Mb/s (64 slots/frame, 8.192 MHz CLK) and 2.048 Mb/s (32 slots/frame, 4.096 MHz CLK) are also fully supported and selected via DR0/DR1 bits in the IMS register.

Does the IDT72V90823PFG support automatic detection of ST-BUS® and GCI frame formats?

Yes, the IDT72V90823PFG automatically detects and configures itself for either ST-BUS® or GCI frame formats when the WFPS pin is LOW. It evaluates the polarity and edge timing of the F0i frame pulse input and aligns internal serial data capture accordingly - rising-edge sampling for GCI, falling-edge for ST-BUS® - without requiring firmware intervention or register configuration.

How is per-channel high-impedance control implemented on the IDT72V90823PFG?

The IDT72V90823PFG provides two-tiered TX output control: global enable/disable via the ODE pin and OSB bit in the IMS register, and per-channel control via the OE bit in each location of the 2,048-entry connection memory. When ODE is LOW and OSB is HIGH, all TX0–TX15 outputs enter high-impedance state; individual channels may then be re-enabled by setting their respective OE bit to HIGH in connection memory.

What is the purpose of the CCO pin on the IDT72V90823PFG?

The CCO (Connection Control Output) pin on the IDT72V90823PFG outputs the CCO bit from each connection memory location once per frame, synchronized to the active serial data rate - 512 bits/frame at 2.048 Mb/s, 1,024 at 4.096 Mb/s, or 2,048 at 8.192 Mb/s. It provides real-time visibility into routing decisions and can drive external status indicators or control logic based on per-channel configuration.

Can the IDT72V90823PFG perform frame offset calibration across multiple input streams?

Yes, the IDT72V90823PFG supports independent frame offset calibration for each of its 16 RX input streams using the frame evaluation (FE/HCLK) pin and programmable frame input offset registers (FOR). Each stream's skew relative to the F0i reference is measured and compensated in increments of 0.5 CLK period, with a maximum adjustment range of +4.5 CLK periods - essential for synchronizing distributed TDM backplane architectures.