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Renesas 72V90823PFG8
- Part No.:
- 72V90823PFG8
- Manufacturer:
- Renesas
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 100-LQFP
- Datasheet:
-
72V90823PFG8.pdf
- Description:
- IC MULTIPLEXER 1 X 16:16 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,943
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Product details
Overview
IDT72V90823PFG8 from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch for ST-BUS®/GCI and wide frame pulse (WFP) interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable or constant throughput delay, IEEE-1149.1 JTAG test port, and 5V-tolerant I/O. It is used in carrier-grade TDM switching systems requiring precise channel-level routing and frame alignment.
For engineers reviewing the IDT72V90823PFG8 datasheet, IDT72V90823PFG8 pinout, IDT72V90823PFG8 application, or IDT72V90823PFG8 equivalent, key selection considerations include supported serial bit rates (2.048/4.096/8.192 Mb/s), microprocessor interface mode (multiplexed/non-multiplexed), per-channel delay configuration (V/C bit), input frame offset calibration capability, and 100-pin TQFP package compatibility with industrial temperature range (–40°C to +85°C).
Technical Context
The IDT72V90823PFG8 implements a dual-mode serial interface supporting both ST-BUS®/GCI (auto-detected polarity) and WFP frame alignment modes, with FE/HCLK used for frame evaluation or HCLK clocking depending on WFPS state. Its internal architecture includes 8 KHz frame-synchronized data memory, connection memory with per-channel control bits (PC, V/C, LPBK, OE, CCO), and parallel-to-serial/serial-to-parallel converters tied to 16 RX/TX streams.
It features programmable stream-level input frame offset compensation (±4.5 CLK periods resolution), automatic frame synchronization detection, and Processor Mode enabling microprocessor-initiated per-channel time-slot writes. The device uses a 3.3 V supply with 5V-tolerant I/O (except TMS/TDI/TRST), and integrates IEEE-1149.1 boundary scan via dedicated TAP pins (TCK, TMS, TDI, TDO, TRST).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Capacity | 2,048 × 2,048 channels at 8.192 Mb/s; scales to 1,024 × 1,024 at 4.096 Mb/s or 512 × 512 at 2.048 Mb/s - defines maximum concurrent TDM channel routing density per data rate. |
| Serial Data Rate | 2.048 / 4.096 / 8.192 Mb/s - determines frame size (32/64/128 slots/frame) and required master clock (4.096 / 8.192 / 16.384 MHz). |
| Throughput Delay | Variable mode: min. 3 time-slots; Constant mode: fixed 1-frame delay - enables voice-optimized low-latency or data-optimized frame-aligned switching. |
| Frame Alignment | Auto-detects ST-BUS®/GCI polarity; supports WFP mode with 4.096 MHz HCLK - eliminates external frame sync logic in multi-chip TDM backplanes. |
| Microprocessor Interface | Intel/Motorola-compatible multiplexed or non-multiplexed 16-bit bus - supports direct integration with legacy DSP/microcontroller buses without glue logic. |
| JTAG Support | IEEE-1149.1 compliant TAP (TCK/TMS/TDI/TDO/TRST) - enables boundary-scan testing and in-system programming of connection memory. |
| Operating Temperature | –40°C to +85°C - qualified for industrial and telecom infrastructure environments including central office and remote terminal applications. |
| Supply Voltage | +3.3 V ± 0.3 V - requires single-supply operation with 5V-tolerant I/O (excluding JTAG pins), simplifying power design vs. mixed-voltage systems. |
Pinout & Package
Package: 100-pin Thin Quad Flatpack (TQFP), 0.50 mm pitch, 14 mm × 14 mm body (order code PF). Pin 1 marked by index notch; IC pin must be tied to GND for normal operation and IEEE-1149.1 compliance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RX0–RX15 | Serial input streams | 16 bidirectional-capable inputs accepting 2.048/4.096/8.192 Mb/s ST-BUS®/GCI or WFP-formatted data; each stream maps to 32/64/128 time slots/frame. |
| TX0–TX15 | Serial output streams | 16 three-state outputs delivering switched time-slot data at identical rate as corresponding RX; controlled globally by ODE and per-channel by connection memory OE bit. |
| F0i, FE/HCLK, WFPS | Frame synchronization interface | F0i accepts 8 kHz frame pulses; FE/HCLK serves as frame evaluation input or 4.096 MHz clock; WFPS selects ST-BUS®/GCI (LOW) or WFP (HIGH) mode. |
| CLK | Master serial clock | Input clock at 4.096/8.192/16.384 MHz - must be exactly 2× selected serial bit rate; drives all serial shift registers and timing units. |
| AD0–AD7, D8–D15, A0–A7, CS, DS/RD, R/W/WR, AS/ALE, IM | Microprocessor interface | Configurable 16-bit parallel bus supporting Intel-style (multiplexed AD0–AD7 + D8–D15) or Motorola-style (non-multiplexed AD0–AD7 + D8–D15 + A0–A7) addressing and control. |
| TCK, TMS, TDI, TDO, TRST | JTAG test port | IEEE-1149.1 boundary scan interface; TRST must be pulsed LOW on power-up to ensure functional mode; TMS/TDI have internal pull-ups. |
| CCO, DTA, ODE, RESET, IC | Control and status signals | CCO outputs per-channel CCO bits synchronously with TX streams; DTA acknowledges microport transfers; ODE enables/disables all TX drivers; RESET (active LOW) clears registers and sets TX to high-Z; IC must be grounded. |
Key Features
| Feature | Design Value |
|---|---|
| Per-channel delay mode selection | V/C bit in connection memory allows independent assignment of variable-delay (voice-optimized) or constant-delay (data-optimized) behavior per time-slot. |
| Input frame offset calibration | Programmable per-stream frame delay offset (±4.5 CLK periods) compensates for inter-stream skew in distributed TDM backplanes. |
| Auto-detect ST-BUS®/GCI interface | Hardware-level polarity and format detection on F0i eliminates software-based frame sync initialization and reduces boot-time latency. |
| Processor Mode operation | Microprocessor writes directly to connection memory locations to inject real-time control/status data onto TX streams - enables dynamic call setup and diagnostics. |
| Memory block programming | IMS register BPD[4:0] + MBP/BPE bits enable full connection memory initialization in two frames - accelerates system boot and reconfiguration. |
| Internal loopback per channel | LPBK bit routes TXn,m → RXn,m internally for per-channel signal integrity verification without external cabling or test equipment. |
Applications
| Telecom Central Office Switching | VoIP Gateway TDM Interface |
|---|---|
|
Use Scenario: Aggregating 16 E1/T1 lines into a centralized TDM fabric for circuit-switched voice routing across PSTN and IP domains. IC Role / Device Role / Timing Role: Time slot interchange switch performing non-blocking 2,048 × 2,048 channel mapping with sub-frame delay control and frame alignment across heterogeneous line cards. Use Value: Maintains strict 125 µs frame integrity while enabling per-channel delay tuning to compensate for variable path lengths between line interface units and DSP farms. |
Use Scenario: Bridging legacy TDM voice traffic (E1) to VoIP media gateways using G.711/G.729 codecs running on DSPs. IC Role / Device Role / Timing Role: Digital switch providing ST-BUS®-compatible serial interface to DSPs and GCI-compatible interface to line interface chips (LICs), with auto-format detection. Use Value: Eliminates manual frame format configuration and reduces firmware complexity by automatically adapting to ST-BUS® or GCI signaling on each RX stream. |
| Wireless Base Station Abis Interface | Industrial TDM Backplane Interconnect |
|
Use Scenario: Routing time-division multiplexed voice and signaling channels between BTS controller and transceiver modules in GSM/UMTS base stations. IC Role / Device Role / Timing Role: High-reliability TSI switch operating in constant-delay mode to preserve Abis frame structure (16 kbit/s per channel, 32-channel frames) across distributed RF units. Use Value: Guarantees deterministic 1-frame throughput delay across all 512 × 512 channels at 2.048 Mb/s - essential for meeting 3GPP-defined Abis timing budgets. |
Use Scenario: Interconnecting multiple DSP blades in ruggedized industrial control systems using time-division multiplexed sensor and actuator data. IC Role / Device Role / Timing Role: Synchronization-aware digital switch supporting variable-path-length compensation via per-stream input frame offset registers. Use Value: Enables use of asymmetric PCB trace lengths across backplane slots while maintaining sample-aligned delivery of 64 kbit/s PCM sensor streams to processing nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar time slot interchange applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT72V90821PFG8 | Same 100-pin TQFP package and core architecture, but limited to 1,024 × 1,024 capacity at 4.096 Mb/s; lacks WFP mode support and CCO output. | Suitable only for mid-scale TDM systems with ≤1,024 channels; cannot replace IDT72V90823PFG8 in 2,048 × 2,048 or WFP-aligned deployments. | Select when cost-sensitive designs require lower channel count and omit WFP or CCO functionality. |
| Cypress CY7C924ADXFT | 48-pin PLCC, 512 × 512 capacity at 2.048 Mb/s; no JTAG, no per-stream frame offset calibration, no Processor Mode; supports only ST-BUS®. | Targeted at simple point-to-point TDM bridging; lacks diagnostic features (loopback, frame eval), scalability, and industrial temp range. | Consider only for legacy replacements where footprint and feature set match older Cypress-based designs. |
Compared with IDT72V90821PFG8 and CY7C924ADXFT, the IDT72V90823PFG8 delivers full 2,048 × 2,048 non-blocking switching, WFP mode support for wide-pulse frame alignment, integrated JTAG for production test, and per-channel Processor Mode - making it the sole option for scalable, field-diagnosable, and standards-flexible telecom infrastructure.
Availability
IDT72V90823PFG8 is available at Aetrix Electronics and suitable for telecom infrastructure, VoIP gateway development, wireless base station design, and industrial TDM backplane interconnect requiring stable component supply across extended product lifecycles.
Supply support for IDT72V90823PFG8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Integrated Device Technology (IDT), now part of Renesas Electronics, is a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions for communications and computing markets.
The IDT72V90823PFG8 belongs to IDT's legacy TSI digital switch product line, designed specifically for carrier-class TDM switching systems requiring precise time-slot routing, frame alignment robustness, and microprocessor configurability in E1/T1/E3/DS3 infrastructure.
FAQ
What is the maximum serial data rate supported by the IDT72V90823PFG8?
The IDT72V90823PFG8 supports a maximum serial data rate of 8.192 Mb/s, enabling 2,048 × 2,048 non-blocking channel switching with 128 time slots per 125 µs frame. At this rate, the required master clock (CLK) is 16.384 MHz. Lower configurations include 4.096 Mb/s (1,024 × 1,024) and 2.048 Mb/s (512 × 512), each with corresponding CLK frequencies of 8.192 MHz and 4.096 MHz respectively. All rates maintain strict frame integrity and per-channel delay control.
How does the IDT72V90823PFG8 handle frame synchronization for mixed ST-BUS® and GCI interfaces?
The IDT72V90823PFG8 automatically detects and identifies incoming frame pulses on the F0i pin as either ST-BUS® or GCI format based on edge polarity and timing relationship to the master clock (CLK). In ST-BUS® mode, it samples on the rising edge of CLK three-quarters into the bit cell; in GCI mode, it samples on the falling edge. This hardware-level auto-detection eliminates software configuration overhead and ensures reliable interoperability with diverse line interface chips without manual format selection.
Can the IDT72V90823PFG8 operate in both variable and constant throughput delay modes simultaneously?
Yes - the IDT72V90823PFG8 supports per-channel selection of variable or constant throughput delay via the V/C bit in each location of its connection memory. This means some time slots can be configured for minimum-latency variable delay (ideal for voice), while others use constant 1-frame delay (required for data frame integrity), all within the same device and frame. The mode is not global; it is independently programmable for each of the 2,048 output channels.
What is the function of the CCO pin on the IDT72V90823PFG8?
The CCO (Control Output) pin on the IDT72V90823PFG8 outputs a serial bitstream derived from the CCO bit in each connection memory location, synchronized to the active serial data rate (4.096/8.192/16.384 Mb/s). It carries one bit per time slot, transmitted one slot before the corresponding TX data - e.g., in 2.048 Mb/s mode, the CCO bit for TX0, CH0 appears during CH31 of the same frame. This enables sideband control signaling alongside primary TDM payload.
Is the IDT72V90823PFG8 compatible with 5 V microprocessor buses?
Yes - all I/O pins on the IDT72V90823PFG8 (except TMS, TDI, and TRST) are 5V tolerant, allowing direct interfacing with 5 V microprocessors or DSPs without level-shifting circuitry. The device itself operates from a 3.3 V supply, and its internal logic is 3.3 V, but input voltage limits extend to 5.5 V. This simplifies integration into mixed-voltage systems common in legacy telecom hardware designs.
72V90823PFG8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- 72V
- Package/Case:
- 100-LQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Multiplexer
- Circuit:
- 1 x 16:16
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TQFP (14x14)
72V90823PFG8 FAQ
1.How can I place an order for 72V90823PFG8 through Aetrix?
Please submit a Request for Quotation (RFQ) for 72V90823PFG8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 72V90823PFG8 reliable?
The price and inventory of 72V90823PFG8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 72V90823PFG8 is usually 5 days.
3.What payment methods are accepted for 72V90823PFG8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 72V90823PFG8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 72V90823PFG8?
72V90823PFG8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 72V90823PFG8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 72V90823PFG8?
For technical support, including 72V90823PFG8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 72V90823PFG8 requirements.
6.How does Aetrix verify that 72V90823PFG8 is sourced from the original manufacturer or authorized distributors?
All 72V90823PFG8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 72V90823PFG8 meets industry standards.
7.What is the process for return or replacement of 72V90823PFG8?
All 72V90823PFG8 units undergo pre-shipment inspection (PSI). If there is an issue with 72V90823PFG8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 72V90823PFG8 part is unused and in its original packaging.
Return procedure for 72V90823PFG8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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