Analog Devices Inc./Maxim Integrated 73S8010C-ILR/F

Overview

73S8010C-ILR/F from Teridian Semiconductor is a single-chip ISO/IEC 7816-3 and EMV 4.0–compliant smart card interface IC. It delivers 3 V or 5 V card power via an inductor-based DC-DC converter, supports I²C host control at 400 kbps, provides automated activation/deactivation sequencing, and integrates 6 kV ESD protection on card I/O lines - deployed in POS terminals, set-top box conditional access slots, and mobile EMV readers.

For engineers reviewing the 73S8010C-ILR/F datasheet, 73S8010C-ILR/F pinout, 73S8010C-ILR/F application, or 73S8010C-ILR/F equivalent, this page delivers verified package mapping (32-QFN), confirmed I²C address configuration (default 0x48), validated emergency deactivation logic (card extraction + VCC/VDD fault), true over-current detection (150 mA limit), and real-world thermal fault response timing - all extracted from Teridian Rev. 1.5 datasheet DS_8010C_024.

Technical Context

The 73S8010C-ILR/F implements a hardware-based ISO-7816-3 activation/deactivation sequencer with deterministic timing: t1 ≥ 0.5 μs for RST low, t4 ≥ 0.5 μs for VCC shutdown, and full deactivation within ~100 μs per EMV 4.0. Its inductive DC-DC converter operates in step-up mode when VDD < VCC setpoint and linear-regulator mode when VDD ≥ VCC (e.g., VDD = 3.6 V, VCC = 3 V).

Host communication uses a fast-mode I²C slave interface with three address-select pins (SAD0–SAD2), enabling up to eight devices on one bus. The status register (bit-mapped) reports PRES, SUPL, PROT, MUTE, EARLY, and ACTIVE states, while the control register configures clock rate (XTALIN/2 to XTALIN), VCC voltage (3 V/5 V), warm reset, and I/O enable - all accessible without firmware overhead.

Key Specifications

Pinout & Package

73S8010C-ILR/F is packaged in a 32-pin QFN (5 mm × 5 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are electrically identical to the SO28 variant but mapped to a denser layout optimized for space-constrained reader designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar smart card interface applications.

Compared with SLB9670HT1.2 and ST8020B, the 73S8010C-ILR/F uniquely combines EMV 4.0–compliant 100 mA card power, hardware sequencer timing, and integrated thermal/fault protection - making it the only option for compact, battery-powered, standards-certified readers requiring zero-host-timing overhead.

Availability

73S8010C-ILR/F is available at Aetrix Electronics and suitable for point-of-sale terminals, set-top box conditional access modules, and mobile EMV readers requiring stable component supply across multi-year production cycles.

Supply support for 73S8010C-ILR/F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Teridian Semiconductor was a fabless analog/mixed-signal IC designer acquired by Maxim Integrated in 2010; its smart card interface portfolio emphasized high-efficiency power delivery and standards-compliant hardware sequencing.

The 73S8010C-ILR/F belongs to Teridian's 73S80xx smart card interface family, engineered specifically for EMV 4.0 and ISO-7816-3 reader applications where minimal MCU intervention, robust fault handling, and compact 5×5 mm QFN packaging are mandatory.

FAQ

What is the default I²C address for the 73S8010C-ILR/F, and how is it configured?

The default 7-bit I²C address for the 73S8010C-ILR/F is 0x48. This is set by the internal pull-up on SAD2 and pull-downs on SAD1/SAD0. Address selection is controlled by three digital inputs (SAD2, SAD1, SAD0) allowing up to eight devices on one bus. The 73S8010C-ILR/F datasheet Table 1 lists all eight possible addresses (0x40 to 0x4E). No external pull-ups are required - configuration is purely pin-strapped.

Does the 73S8010C-ILR/F support both 3 V and 5 V smart cards, and how is the voltage selected?

Yes, the 73S8010C-ILR/F supports both 3 V and 5 V smart cards. Voltage selection is controlled by bit 2 of the Host Control Register: setting the bit configures VCC = 3 V, clearing it sets VCC = 5 V. The DC-DC converter dynamically adjusts regulation mode - operating as a step-up converter when VDD < VCC setpoint and as a linear regulator when VDD ≥ VCC (e.g., VDD = 3.6 V, VCC = 3 V). This ensures compliance with ISO-7816-3 voltage tolerances.

How does the 73S8010C-ILR/F handle card removal during an active session?

The 73S8010C-ILR/F performs automatic emergency deactivation upon card removal. The PRES pin detects extraction, triggering the hardware sequencer to execute the full ISO-7816-3 deactivation sequence: RST goes low within ≥0.5 μs, CLK low within ≥7.5 μs, I/O disabled, and VCC shut down within ≥0.5 μs - completing in ~100 μs. This action also asserts the INT pin and sets the PROT bit in the status register, ensuring host awareness without software polling.

What external components are required for the 73S8010C-ILR/F DC-DC converter?

The 73S8010C-ILR/F DC-DC converter requires three external components: a 10 μH inductor (rated ≥400 mA) connected between LIN and VDD; a 100 nF + 10 μF ceramic/electrolytic capacitor pair on VDD near the LIN pin; and a VCC output filter capacitor - 1 μF for ISO-7816-3 or 3.3 μF X5R/X7R (ESR < 100 mΩ) for EMV 4.0 compliance. No transformer or additional regulators are needed.

Is the 73S8010C-ILR/F pin-compatible with other members of the 73S80xx family, such as the 73S8009?

No, the 73S8010C-ILR/F is not pin-compatible with the 73S8009. While both belong to the same family and share functional similarities, the 73S8009 uses a 28-pin SO package with different pin assignments (e.g., LIN is pin 5 in SO vs. pin 2 in QFN), distinct address pin locations, and no VDDF_ADJ pin. The 73S8010C-ILR/F's 32-QFN footprint and signal mapping are unique to its variant - PCB layout must be designed specifically for 73S8010C-ILR/F.