Analog Devices Inc./Maxim Integrated 73S8010R-IM/F

Overview

73S8010R-IM/F from Teridian Semiconductor is a single-chip ISO/EMV-compliant smart card interface IC with integrated LDO regulator, 400 kbps I²C host interface, true 150 mA over-current detection, 3 V/5 V selectable card voltage, and emergency deactivation on card removal or fault. It serves as the electrical bridge between microcontrollers and contact smart cards in secure transaction systems.

For engineers reviewing the 73S8010R-IM/F datasheet, 73S8010R-IM/F pinout, 73S8010R-IM/F application, or 73S8010R-IM/F equivalent, this page delivers verified pin functions, real-world fault-handling behavior, LDO-supplied VCC regulation specs, I²C address configuration options, and validated alternative parts for conditional access and payment terminal designs.

Technical Context

The 73S8010R-IM/F implements a hardware-based ISO-7816-3 activation/deactivation sequencer with autonomous emergency shutdown triggered by VDD, VPC, VCC, over-current (150 mA), or die temperature (>145 °C) faults. Its embedded LDO regulator accepts 4.75–5.5 V on VPC and delivers regulated 3 V or 5 V to VCC with ±0.1 V ripple tolerance in active mode.

Host communication uses a fast-mode I²C slave interface (400 kbps) with three address-select pins (SAD0–SAD2) enabling up to eight devices on one bus. Card clock generation supports either internal crystal oscillator (XTALIN/XTALOUT) or external clock input up to 27 MHz, with programmable divisors (ClkSel1/ClkSel2 bits) selecting /2, /4, /8, or direct pass-through.

Key Specifications

Pinout & Package

73S8010R-IM/F is packaged in a 32-pin QFN (5 mm × 5 mm × 0.8 mm) with wettable flanks, RoHS-compliant and lead-free. Pin numbering follows QFN32 layout per Figure 2 of DS_8010R_022 Rev. 1.6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar smart card interface applications.

Compared with SLB9670 and TDA8020, the 73S8010R-IM/F offers superior integration (LDO + sequencer + fault logic in one QFN32), field-proven EMV 4.0 compliance, and flexible VDD fault adjustment-making it optimal for new industrial and financial terminal designs requiring compact, robust, and standards-certified smart card interfacing.

Availability

73S8010R-IM/F is available at Aetrix Electronics and suitable for set-top box conditional access, point-of-sale terminals, physical access control systems, and multi-card reader applications requiring stable component supply, long-term lifecycle assurance, and industrial-grade reliability.

Supply support for 73S8010R-IM/F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Teridian Semiconductor was a fabless analog/mixed-signal IC designer specializing in metering, power management, and secure interface solutions before its acquisition by Maxim Integrated in 2011.

The 73S8010R-IM/F belongs to Teridian's smart card interface product line, engineered specifically for EMV-compliant financial terminals and conditional access systems demanding high integration, low EMI, and fail-safe power control.

FAQ

What is the function of the VDDF_ADJ pin on the 73S8010R-IM/F?

The VDDF_ADJ pin on the 73S8010R-IM/F allows external resistor networks to customize the VDD undervoltage fault threshold. By default, the device trips at 2.15–2.4 V; connecting a resistor divider between VDDF_ADJ and GND shifts this threshold to match the host microcontroller's operating voltage window. This feature ensures coordinated system-level shutdown during brown-out conditions and is documented in Table 8 of the 73S8010R-IM/F datasheet.

Does the 73S8010R-IM/F support both 3 V and 5 V smart cards?

Yes, the 73S8010R-IM/F supports both 3 V and 5 V smart cards via software-selectable VCC output. Bit 2 of the Control Register determines the LDO output voltage: reset = 5 V, set = 3 V. The device maintains tight regulation (±0.1 V) under 90 mA load and meets ISO-7816-3 VCC slew rate requirements (0.02–0.08 V/µs) for both voltages, as verified in Table 4 of the 73S8010R-IM/F datasheet.

How does the 73S8010R-IM/F handle card removal during an active session?

The 73S8010R-IM/F performs emergency deactivation upon card removal: the PRES pin transition triggers immediate VCC ramp-down (0.025–0.08 V/µs), disables CLK and RST outputs, and asserts the INT pin. This hardware-automated sequence complies with ISO-7816-3 deactivation timing and prevents electrical stress or data corruption. Fault status is latched in the Status Register (bit PROT) until read by the host via I²C.

What clock sources does the 73S8010R-IM/F accept for generating the card clock signal?

The 73S8010R-IM/F accepts two clock sources: an external crystal (connected between XTALIN and XTALOUT) or an external clock signal applied to XTALIN while leaving XTALOUT unconnected. The internal oscillator supports crystals up to 27 MHz, and the CLKSEL1/CLKSEL2 bits in the Control Register select divisor ratios (/2, /4, /8, or direct pass-through), enabling precise card clock rates from 1 MHz to 27 MHz as defined in Table 11 of the 73S8010R-IM/F datasheet.

Is the 73S8010R-IM/F pin-compatible with the TDA8020?

No, the 73S8010R-IM/F is not pin-compatible with the TDA8020. While firmware and register maps are compatible, the 73S8010R-IM/F uses a 32-pin QFN or 28-pin SO package with different pin assignments-including dedicated VDDF_ADJ, AUX2UC, and updated SAD pin locations. Migration requires PCB layout revision. However, functional equivalence and register compatibility simplify firmware reuse across both devices.