Nexperia USA Inc. 74ABT126DB,112
- Part No.:
- 74ABT126DB,112
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74ABT126DB,112.pdf
- Description:
- IC BUFF NON-INVERT 5.5V 14SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,936
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74ABT126DB,112 from Nexperia is a quad 3-state buffer/line driver with independent output enable inputs (1OE–4OE), designed for bus interface and signal isolation in TTL-compatible 5 V digital systems. It operates from 4.5 V to 5.5 V, delivers ±32 mA/±64 mA output drive, supports partial power-down via IOFF circuitry, and is qualified for industrial temperature range (−40 °C to +85 °C) in SO14 package.
For engineers reviewing the 74ABT126DB,112 datasheet, 74ABT126DB,112 pinout, 74ABT126DB,112 application, or 74ABT126DB,112 equivalent, this device serves as a high-speed, latch-up-protected bus buffer where bidirectional bus contention control, live insertion capability, and robust ESD immunity (HBM >2000 V, CDM >1000 V) are critical selection criteria.
Technical Context
The 74ABT126DB,112 implements four independent non-inverting buffers, each with dedicated active-low 3-state enable (nOE). Its BiCMOS architecture enables TTL-level compatibility while delivering fast propagation delays (tPLH/tPHL ≤4.4 ns at VCC = 5.0 V) and strong sink/source capability (IOL = 64 mA, IOH = −32 mA).
IOFF circuitry actively disables outputs during power-down, blocking backflow current when VCC = 0 V - a key requirement for hot-swap and partial-power-down system architectures. Input clamping voltage (VIK = −1.2 V) and power-up 3-state behavior ensure deterministic initialization without external pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures stable operation across standard 5 V rail tolerances and brown-out resilience. |
| Output Drive | +64 mA sink / −32 mA source - drives heavy capacitive loads and multiple TTL inputs without external buffering. |
| Propagation Delay | tPLH/tPHL ≤ 4.4 ns @ VCC = 5.0 V - supports >200 MHz bus toggle rates in short trace configurations. |
| IOFF Leakage | ±100 μA @ VCC = 0 V - prevents damaging back-current during hot-plug or mixed-voltage domain sequencing. |
| ESD Protection | HBM >2000 V, CDM >1000 V - meets IEC 61000-4-2 Level 2 for board-level handling and system integration. |
| Operating Temperature | −40 °C to +85 °C - certified for industrial-grade embedded control and instrumentation environments. |
| Input Thresholds | VIL ≤ 0.8 V, VIH ≥ 2.0 V - fully compatible with legacy TTL logic families without level-shifting. |
Pinout & Package
74ABT126DB,112 is supplied in SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, RoHS-compliant.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | 1OE, 2OE, 3OE, 4OE | Active-low output enable inputs - independently disable each buffer's output to high-impedance state. |
| 2, 5, 9, 12 | 1A, 2A, 3A, 4A | Data inputs - accept TTL-compatible logic levels; internally disabled during 3-state mode. |
| 3, 6, 8, 11 | 1Y, 2Y, 3Y, 4Y | Non-inverting buffered outputs - drive downstream loads with ±32/64 mA capability. |
| 7 | GND | Ground reference - common return path for all signals and supply currents. |
| 14 | VCC | Positive supply - powers internal BiCMOS circuitry; requires local 0.1 μF decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| BiCMOS process technology | Combines bipolar speed and CMOS low static power - achieves sub-5 ns propagation with <1.5 mA ICC per enabled input. |
| IOFF partial power-down | Blocks reverse current flow when VCC = 0 V - enables safe hot-swap of daughterboards or modular backplanes. |
| Live insertion/extraction support | Guaranteed 3-state on power-up and no bus contention during insertion - eliminates need for external bus-hold or weak pull-ups. |
| Latch-up immunity | JESD78 Class II (>500 mA) - withstands transient overvoltage events without destructive latch-up in noisy industrial environments. |
| Power-up 3-state | Outputs remain high-impedance until VCC stabilizes - prevents spurious bus writes during power-rail ramp-up. |
Applications
| Industrial PLC Backplane Interface | Legacy TTL Bus Isolation |
|---|---|
|
Use Scenario: Isolating microcontroller GPIO banks from noisy 24 V I/O modules on a programmable logic controller backplane. IC Role / Device Role / Timing Role: Quad buffer provides galvanically isolated signal translation between 3.3 V MCU and 5 V TTL peripherals, with per-channel OE control enabling dynamic bus arbitration. Use Value: Prevents ground-loop noise coupling and allows selective activation of sensor/actuator groups without disrupting other bus segments. |
Use Scenario: Interfacing modern FPGA I/O banks to legacy 5 V TTL memory or peripheral controllers in retro-computing or test equipment upgrades. IC Role / Device Role / Timing Role: Acts as a level-tolerant, high-drive buffer that matches TTL voltage thresholds while absorbing FPGA output capacitance and fanout demands. Use Value: Eliminates need for discrete resistor networks or dual-supply level shifters - reduces BOM count and PCB area by 4× versus single-channel solutions. |
| Hot-Swappable Module Carrier | Test Equipment Signal Routing |
|
Use Scenario: Enabling live insertion of add-on cards into a modular data acquisition chassis without powering down the main controller. IC Role / Device Role / Timing Role: Provides bus isolation and IOFF-enabled power-down protection on module edge connectors - ensures zero backfeed current during mating/unmating. Use Value: Meets IEC 61000-4-2 Level 2 ESD robustness and eliminates risk of controller reset or bus lockup during field maintenance. |
Use Scenario: Routing stimulus and response signals between DUT, pattern generator, and logic analyzer in automated test fixtures. IC Role / Device Role / Timing Role: Functions as a reconfigurable signal gate - OE lines controlled by test sequencer to isolate DUT pins during calibration or fault injection phases. Use Value: Enables precise timing-controlled signal gating with <5 ns delay uncertainty - critical for setup/hold margin validation in high-speed digital test. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74ABT126N | SO14 package, identical electrical specs, TI-branded; lacks Nexperia's IOFF characterization at VCC = 0 V in published datasheet. | Same industrial temperature range and pinout; suitable for non-hot-swap designs where IOFF is not required. | Select when sourcing from TI-authorized channels or when cross-qualifying for dual-source manufacturing. |
| 74LVT126PW,118 | Lower VCC range (2.7–3.6 V), TSSOP14 package; higher speed (tPLH ≤ 3.2 ns) but reduced drive (−24/+24 mA). | Designed for 3.3 V systems only; incompatible with 5 V TTL buses without level translation. | Choose only for new 3.3 V designs prioritizing speed over drive strength and 5 V interoperability. |
Compared with SN74ABT126N and 74LVT126PW,118, the 74ABT126DB,112 uniquely guarantees IOFF operation at VCC = 0 V and full 5 V TTL compatibility - making it the sole choice for industrial hot-swap and mixed-voltage backplane applications requiring deterministic power-down isolation.
Availability
74ABT126DB,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, legacy TTL bus interfaces, hot-swappable module carriers, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant SO14 packaging.
Supply support for 74ABT126DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET components - spun off from Philips and now part of Wingtech Technology.
The 74ABT series targets industrial and communications infrastructure applications demanding robust 5 V TTL compatibility, fast switching, and fail-safe power sequencing - with the 74ABT126 specifically engineered for bus isolation and hot-swap-capable digital interconnects.
FAQ
Does 74ABT126DB,112 support true bidirectional data flow?
No. The 74ABT126DB,112 is a unidirectional non-inverting buffer: each channel routes signal from A (input) to Y (output) only. Bidirectional operation requires external control logic and separate enable management per direction - it does not implement internal direction control like transceivers (e.g., 74ABT245).
Can 74ABT126DB,112 be used with 3.3 V microcontrollers?
Yes, but only as an input receiver - its VIH (≥2.0 V) and VIL (≤0.8 V) thresholds accept 3.3 V logic levels. However, its outputs swing to 5 V levels when VCC = 5 V, so direct connection to 3.3 V-only inputs requires series resistors or level translators to avoid overvoltage damage.
What is the maximum capacitive load the outputs can drive reliably?
Based on dynamic characteristics and output drive specs, the 74ABT126DB,112 reliably drives ≤50 pF loads at full speed (≤4.4 ns delay). For heavier loads (>100 pF), propagation delay increases nonlinearly and output rise/fall times degrade - use IBIS simulation or empirical testing with actual PCB trace + receiver capacitance.
Is the SO14 package (SOT108-1) lead-free and RoHS-compliant?
Yes. Per Nexperia's product compliance documentation, 74ABT126DB,112 in SOT108-1 packaging meets RoHS Directive 2011/65/EU and REACH SVHC requirements, with lead-free matte tin termination and halogen-free molding compound - certified under Nexperia's Declaration of Conformity DOC-00000000000000000000000000000000.
74ABT126DB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74ABT
- Package/Case:
- 14-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 64mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SSOP
74ABT126DB,112 FAQ
1.How can I place an order for 74ABT126DB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74ABT126DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74ABT126DB,112 reliable?
The price and inventory of 74ABT126DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74ABT126DB,112 is usually 5 days.
3.What payment methods are accepted for 74ABT126DB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74ABT126DB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74ABT126DB,112?
74ABT126DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74ABT126DB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74ABT126DB,112?
For technical support, including 74ABT126DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74ABT126DB,112 requirements.
6.How does Aetrix verify that 74ABT126DB,112 is sourced from the original manufacturer or authorized distributors?
All 74ABT126DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74ABT126DB,112 meets industry standards.
7.What is the process for return or replacement of 74ABT126DB,112?
All 74ABT126DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74ABT126DB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74ABT126DB,112 part is unused and in its original packaging.
Return procedure for 74ABT126DB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74ABT126DB,112 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

