Nexperia USA Inc. 74ABT126PW,118
- Part No.:
- 74ABT126PW,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74ABT126PW,118.pdf
- Description:
- IC BUFF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74ABT126PW,118 from Nexperia is a quad 3-state buffer/line driver in TSSOP14 package, operating at 4.5–5.5 V supply, delivering ±32 mA/±64 mA output drive, with IOFF partial power-down protection and TTL-level compatibility. It serves as a bidirectional bus interface element in industrial control backplanes and legacy data acquisition systems requiring hot-swap capability.
For engineers reviewing the 74ABT126PW,118 datasheet, 74ABT126PW,118 pinout, 74ABT126PW,118 application, or 74ABT126PW,118 equivalent, this device is selected for its guaranteed 3-state isolation during power sequencing, live insertion support, and robust ±500 mA latch-up immunity - critical for mixed-voltage board-level interconnects.
Technical Context
The 74ABT126PW,118 implements four independent non-inverting buffers, each with dedicated active-low output enable (nOE) controlling high-impedance OFF-state entry. Its BiCMOS architecture enables fast propagation delays (tPLH/tPHL ≤ 4.4 ns @ VCC = 5.0 V) while sustaining rail-to-rail input tolerance (VI = –1.2 V to +7.0 V).
IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±100 μA and enabling safe partial power-down operation. Input clamping diodes and ESD structures meet HBM >2000 V and CDM >1000 V per JS-001/JS-002.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 4.5 V to 5.5 V - ensures stable operation across industrial 5 V rails with ±10 % tolerance. |
| Output drive | +64 mA sink / –32 mA source - supports driving heavy capacitive loads (e.g., 50 pF buses) without signal degradation. |
| Propagation delay | tPLH/tPHL ≤ 4.4 ns @ VCC = 5.0 V - enables reliable timing in sub-200 MHz synchronous bus interfaces. |
| IOFF leakage | ±100 μA @ VCC = 0 V - prevents damaging back-current during hot-swap or staggered power-up sequences. |
| ESD rating | HBM >2000 V, CDM >1000 V - meets IEC 61000-4-2 Level 2 system-level robustness requirements. |
| Latch-up immunity | JESD78 >500 mA - guarantees immunity to destructive latch-up under transient overvoltage events. |
| Operating temperature | –40 °C to +85 °C - qualified for extended industrial ambient conditions without derating. |
Pinout & Package
TSSOP14 package (SOT402-1): plastic thin shrink small outline, 14-pin, 4.4 mm body width, 0.65 mm lead pitch, gull-wing leads, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE₁–nOE₄ | Active-low output enable inputs - each controls one buffer's 3-state output independently. |
| 2, 5, 9, 12 | nA₁–nA₄ | Data inputs - accept TTL-compatible logic levels (VIL ≤ 0.8 V, VIH ≥ 2.0 V) with clamping. |
| 3, 6, 8, 11 | nY₁–nY₄ | Buffered non-inverting outputs - deliver full-rail swing with ±64 mA sink capability. |
| 7 | GND | Ground reference - common return path for all inputs, outputs, and internal bias networks. |
| 14 | VCC | Positive supply - powers internal BiCMOS logic and output stages; supports IOFF when at 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| BiCMOS process technology | Combines bipolar speed and CMOS low static power - achieves <4.5 ns propagation with <1.5 mA ICC per enabled buffer. |
| Power-up 3-state | Outputs remain in high-impedance state until VCC stabilizes - prevents bus contention during power-on reset. |
| Live insertion/extraction support | IOFF + ESD hardening allows safe hot-plug into powered backplanes without system interruption. |
| TTL input compatibility | Accepts standard TTL logic thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V) without external level-shifting. |
| Input disable in 3-state mode | Inputs are electrically isolated when outputs are disabled - eliminates floating input noise coupling. |
Applications
| Industrial Backplane Interface | Legacy Data Acquisition Bus |
|---|---|
|
Use Scenario: Isolating microcontroller GPIO banks from shared 5 V parallel data buses in programmable logic controllers. IC Role / Device Role / Timing Role: Quad buffer provides direction-controlled, 3-state-isolated signal translation between MCU and multi-drop peripheral bus. Use Value: Prevents bus contention during firmware updates and enables deterministic read/write arbitration via independent nOE control. |
Use Scenario: Driving long-trace analog-to-digital converter (ADC) control lines in factory-floor sensor nodes. IC Role / Device Role / Timing Role: Line driver strengthens weak MCU output signals to meet setup/hold timing of 12-bit SAR ADCs over 15 cm PCB traces. Use Value: ±64 mA sink capability maintains clean 0 V LOW and sharp edge rates despite 30 pF trace + input capacitance loading. |
| Hot-Swappable Module Carrier | Test Equipment Signal Conditioning |
|
Use Scenario: Enabling safe insertion/removal of daughter cards in powered rack-mounted instrumentation chassis. IC Role / Device Role / Timing Role: 3-state buffer isolates card-local logic from main backplane during mechanical mating/unmating. Use Value: IOFF protection limits backfeed current to <100 μA when VCC is unpowered, eliminating risk of damage to host controller. |
Use Scenario: Level-shifting and fan-out buffering for digital trigger and clock distribution in automated test equipment (ATE). IC Role / Device Role / Timing Role: Non-inverting buffer replicates precise timing edges across multiple instrument subsystems with matched skew. Use Value: Propagation delay matching (Δt < 0.5 ns between channels) ensures sub-nanosecond synchronization across trigger paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC126PW,118 | Lower supply range (1.65–3.6 V), lower drive (±24 mA), no IOFF, higher input threshold (VIH ≥ 2.0 V @ VCC = 3.3 V) | Not suitable for 5 V legacy systems; requires level-shifting if interfacing with TTL or 5 V peripherals. | Select only for new 3.3 V designs where power efficiency outweighs 5 V interoperability. |
| SN74ABT126DBR | SOIC-14 (SOT108-1) package, identical electrical specs, same IOFF and drive strength | Same functional behavior but larger footprint; preferred where hand-soldering or thermal mass is prioritized over density. | Choose for prototyping or repair where SO14 footprint matches legacy board layouts. |
Compared with 74LVC126PW,118 and SN74ABT126DBR, the 74ABT126PW,118 uniquely balances 5 V TTL compatibility, hot-swap safety via IOFF, and TSSOP density - making it the sole option for space-constrained industrial backplanes requiring native 5 V operation and live insertion.
Availability
74ABT126PW,118 is available at Aetrix Electronics and suitable for industrial backplane interfaces, legacy data acquisition buses, hot-swappable module carriers, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74ABT126PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, high-reliability logic, discrete, and MOSFET solutions for industrial, automotive, and computing markets.
The 74ABT series targets robust 5 V digital interfacing in harsh environments, emphasizing IOFF protection, latch-up immunity, and TTL compatibility for legacy system upgrades and long-lifecycle industrial deployments.
FAQ
Does the 74ABT126PW,118 support mixed-voltage operation between 3.3 V and 5 V domains?
No - it operates strictly at 4.5–5.5 V and accepts TTL-level inputs (VIL ≤ 0.8 V, VIH ≥ 2.0 V). While its inputs tolerate up to +7.0 V, it lacks level-shifting circuitry and cannot safely drive or be driven by 3.3 V logic without external resistive or active translators.
What is the maximum capacitive load the 74ABT126PW,118 can drive while maintaining specified timing?
Per Nexperia's test conditions in Table 9, the device is characterized with 50 pF load and 500 Ω termination. At 5.0 V supply, it sustains tPLH/tPHL ≤ 4.4 ns and output rise/fall times ≤ 2.5 ns under these conditions - confirming reliable operation on typical PCB traces plus IC input capacitance totaling ≤ 50 pF.
How does the IOFF feature behave when VCC is ramping from 0 V to 5 V?
IOFF activates when VCC drops below ~2.1 V and remains active until VCC exceeds ~2.1 V. During that transition window, output leakage is limited to ±100 μA regardless of output voltage, preventing back-current flow even if outputs are pulled HIGH by external circuitry before VCC stabilizes.
Can all four buffers be enabled simultaneously without exceeding thermal limits?
Yes - at 5.5 V and 25 °C, total ICC is ≤ 250 μA in 3-state mode and ≤ 1.5 mA per enabled buffer (max 6 mA total). With θJA ≈ 150 K/W for TSSOP14, power dissipation remains <35 mW, resulting in negligible junction temperature rise (<6 °C) - well within the 150 °C absolute max rating.
74ABT126PW,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74ABT
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 64mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
74ABT126PW,118 FAQ
1.How can I place an order for 74ABT126PW,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74ABT126PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74ABT126PW,118 reliable?
The price and inventory of 74ABT126PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74ABT126PW,118 is usually 5 days.
3.What payment methods are accepted for 74ABT126PW,118?
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74ABT126PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74ABT126PW,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74ABT126PW,118?
For technical support, including 74ABT126PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74ABT126PW,118 requirements.
6.How does Aetrix verify that 74ABT126PW,118 is sourced from the original manufacturer or authorized distributors?
All 74ABT126PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74ABT126PW,118 meets industry standards.
7.What is the process for return or replacement of 74ABT126PW,118?
All 74ABT126PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74ABT126PW,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74ABT126PW,118 part is unused and in its original packaging.
Return procedure for 74ABT126PW,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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