Texas Instruments 74AC11238N
- Part No.:
- 74AC11238N
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- -
- Datasheet:
-
74AC11238N.pdf
- Description:
- IC DECODER/DRIVER AC SERIES
- Quantity:
- Payment:

- Shipping:

Inventory:1,771
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AC11238N from Texas Instruments is a high-speed 3-to-8 line decoder/demultiplexer with three enable inputs (two active-low, one active-high), designed for memory decoding and data routing in systems requiring sub-10 ns propagation delay at 5 V. It features flow-through pinout, center-pin VCC/GND for noise reduction, EPIC CMOS process, and operates from −40°C to 85°C.
For engineers reviewing the 74AC11238N datasheet, 74AC11238N pinout, 74AC11238N application, or 74AC11238N equivalent, key selection criteria include propagation delay (tPLH/tPHL ≤ 8.5 ns @ 5 V), output drive (±24 mA), input voltage thresholds (VIL = 1.35 V, VIH = 3.15 V @ VCC = 4.5 V), and 300-mil plastic DIP package compatibility.
Technical Context
The 74AC11238N implements positive-logic 3-input binary decoding with three independent enables (G1, G2A, G2B) controlling output activation. Its flow-through architecture routes A, B, C select lines to pins 1–3 and outputs Y0–Y7 to pins 4–11 and 15–16, minimizing trace crossings on PCBs.
It uses TI's EPIC 1-μm CMOS process, delivering 500-mA latch-up immunity at 125°C and operating across 3 V to 5.5 V supply range. Enable logic allows cascading up to 24-line decoding without external inverters and supports demultiplexing by repurposing G1 as a data input.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Propagation Delay | tPLH/tPHL ≤ 8.5 ns @ VCC = 5 V - enables use in high-speed memory systems where decoder delay must be negligible vs. memory access time. |
| Supply Voltage Range | 3 V to 5.5 V - supports mixed-voltage system interfacing and legacy 5 V TTL-compatible operation. |
| Output Drive | ±24 mA @ VCC = 4.5 V - sufficient to directly drive multiple TTL loads or fan-out to 10+ AC inputs without buffers. |
| Input Thresholds | VIH = 3.15 V, VIL = 1.35 V @ VCC = 4.5 V - ensures robust noise margin (>1.3 V) in noisy industrial environments. |
| Operating Temperature | −40°C to +85°C - qualified for commercial/industrial embedded applications including baseband processing and control logic. |
| Power Dissipation Cap. | Cpd = 44 pF @ 5 V, 1 MHz - enables accurate dynamic power estimation in clocked decode trees. |
Pinout & Package
74AC11238N is supplied in a 16-pin plastic dual in-line package (PDIP), 300-mil width, with center-aligned VCC (pin 16) and GND (pin 8) to suppress simultaneous switching noise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Select Inputs A, B, C | Binary address inputs determining active output Y0–Y7; routed to left side for flow-through layout. |
| 4–7, 15, 16, 9, 10 | Outputs Y0–Y7 | Active-high decoded outputs; Y0–Y3 on lower-left, Y4–Y7 on upper-right for minimal trace overlap. |
| 11, 10, 9 | Enable Inputs G1, G2A, G2B | G1 (active-high), G2A/G2B (active-low); enable logic allows hierarchical decoding without external gates. |
| 8 | GND | Ground reference; center-positioned to reduce ground bounce during multi-output switching. |
| 16 | VCC | Positive supply; center-positioned opposite GND to form low-inductance power pair for high-frequency stability. |
Key Features
| Feature | Design Value |
|---|---|
| Flow-through architecture | Input (A/B/C) and output (Y0–Y7) pins arranged to minimize PCB trace length and crosstalk in dense decode arrays. |
| Center-pin VCC/GND | Reduces simultaneous switching noise by lowering power/ground loop inductance-critical for sub-10 ns timing integrity. |
| Three enable inputs | Two active-low (G2A, G2B) and one active-high (G1) allow flexible cascading: 24-line decode without inverters; 32-line with one inverter. |
| Demultiplexing capability | G1 can serve as data input while A/B/C act as select lines-enables single-chip 1-to-8 demux without reconfiguration. |
| EPIC CMOS process | Delivers 500-mA latch-up immunity at 125°C and stable AC performance across full industrial temperature range. |
Applications
| Memory Address Decoding | Bus Interface Logic |
|---|---|
|
Use Scenario: Selecting one of eight memory banks in a 64 KB microcontroller system with fast SRAM. IC Role / Device Role / Timing Role: 3-to-8 line decoder providing chip-select signals synchronized to address bus transitions. Use Value: Propagation delay ≤8.5 ns ensures decoder overhead remains below 10% of typical 100 ns SRAM access time. |
Use Scenario: Routing control signals from a shared system bus to eight peripheral devices (ADCs, DACs, GPIO expanders). IC Role / Device Role / Timing Role: Demultiplexer enabling time-multiplexed access to peripherals without bus contention. Use Value: ±24 mA drive strength directly interfaces with standard TTL/CMOS inputs, eliminating level-shifter requirements. |
| Industrial PLC I/O Expansion | Digital Test Equipment Signal Routing |
|
Use Scenario: Expanding discrete I/O points in programmable logic controllers using modular backplane architecture. IC Role / Device Role / Timing Role: Cascaded decoder enabling 24-bit address space via G1/G2A/G2B enables without external logic. Use Value: −40°C to +85°C rating and 500-mA latch-up immunity ensure reliability in uncontrolled cabinet environments. |
Use Scenario: Configuring signal paths in automated test equipment (ATE) for parallel stimulus/response channel selection. IC Role / Device Role / Timing Role: High-speed demux routing clock/data pairs to DUT interface sites under FPGA control. Use Value: Flow-through pinout simplifies controlled-impedance routing on high-density ATE backplanes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74ACT11238N | Higher drive (±24 mA vs. ±24 mA same), but tighter VIH/VIL thresholds (3.5 V / 1.5 V @ 5 V) and faster tPHL (≤7.3 ns). | Better suited for systems with strict noise margins and sub-8 ns timing budgets; not drop-in due to input threshold shift. | Select when interfacing with low-noise 5 V CMOS sources and requiring <8 ns worst-case delay. |
| SN74HC238N | Slower (tPHL ≤ 26 ns @ 5 V), lower drive (±4 mA), wider VCC range (2–6 V), but lower static current (ICC < 4 μA). | Targeted at battery-powered or low-power decode tasks where speed is secondary to quiescent consumption. | Choose for cost-sensitive, low-speed industrial controls where 74AC11238N's speed and drive are unnecessary. |
Compared with 74ACT11238N, the 74AC11238N offers more relaxed input thresholds for legacy TTL compatibility; versus SN74HC238N, it delivers 3× faster propagation and 6× higher output current-critical for driving terminated transmission lines or multiple loads in real-time systems.
Availability
74AC11238N is available at Aetrix Electronics and suitable for high-speed memory decoding, industrial PLC I/O expansion, and digital test equipment signal routing requiring stable component supply and long-term industrial lifecycle support.
Supply support for 74AC11238N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.
The 74AC logic family was engineered for high-speed, low-noise digital systems requiring TTL-compatible voltage levels and sub-10 ns timing-targeting memory subsystems, data routers, and real-time control logic.
FAQ
What is the maximum propagation delay of the 74AC11238N at 5 V?
The 74AC11238N has a maximum propagation delay of 8.5 ns (tPLH) and 10.2 ns (tPHL) at VCC = 5 V and TA = 25°C, measured from any select or enable input to any Y output. This specification ensures the 74AC11238N introduces negligible latency in high-speed memory decode paths where access times are ≥100 ns.
Does the 74AC11238N support demultiplexing functionality?
Yes-the 74AC11238N supports demultiplexing by using G1 as a data input while A, B, and C serve as select lines. When G2A and G2B are asserted, the state of G1 appears on the selected Y output, enabling 1-to-8 signal distribution without external reconfiguration. This behavior is explicitly documented in the functional description and application diagrams of the 74AC11238N datasheet.
What package type is used for the 74AC11238N?
The 74AC11238N is packaged in a 16-pin plastic dual in-line package (PDIP) with 300-mil body width and through-hole mounting. Pin 8 is GND and pin 16 is VCC, positioned centrally to minimize switching noise-a defining mechanical feature confirmed in the "PACKAGE OPTION ADDENDUM" and top-view diagrams of the 74AC11238N datasheet.
Can the 74AC11238N be cascaded to decode more than 8 lines?
Yes-the 74AC11238N supports cascading via its three enable inputs (G1, G2A, G2B). Two active-low and one active-high enables allow implementation of a 24-line decoder without external inverters, and a 32-line decoder with only one external inverter. This capability is verified in Figures 2 and 3 of the 74AC11238N datasheet and forms part of its core architectural advantage.
What is the latch-up immunity specification for the 74AC11238N?
The 74AC11238N provides 500-mA typical latch-up immunity at 125°C, as specified in the "Features" section and absolute maximum ratings table of its datasheet. This performance stems from Texas Instruments' EPIC (Enhanced-Performance Implanted CMOS) 1-μm process and ensures robust operation in thermally demanding industrial environments where transient currents could otherwise trigger parasitic SCR conduction.
74AC11238N Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- -
- Circuit:
- -
- Independent Circuits:
- -
- Current - Output High, Low:
- -
- Voltage Supply Source:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
74AC11238N FAQ
1.How can I place an order for 74AC11238N through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AC11238N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AC11238N reliable?
The price and inventory of 74AC11238N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AC11238N is usually 5 days.
3.What payment methods are accepted for 74AC11238N?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AC11238N transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AC11238N?
74AC11238N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AC11238N order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AC11238N?
For technical support, including 74AC11238N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AC11238N requirements.
6.How does Aetrix verify that 74AC11238N is sourced from the original manufacturer or authorized distributors?
All 74AC11238N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AC11238N meets industry standards.
7.What is the process for return or replacement of 74AC11238N?
All 74AC11238N units undergo pre-shipment inspection (PSI). If there is an issue with 74AC11238N, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AC11238N part is unused and in its original packaging.
Return procedure for 74AC11238N:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AC11238N Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

