Nexperia USA Inc. 74AHC125D,118
- Part No.:
- 74AHC125D,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74AHC125D,118.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:4,597
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Product details
Overview
74AHC125D,118 from Nexperia is a quad CMOS buffer/line driver with 3-state outputs, controlled by active-low output enable inputs (1OE–4OE). It operates from 2.0 V to 5.5 V, features overvoltage-tolerant inputs up to 5.5 V, and delivers balanced propagation delays as low as 3.0 ns (VCC = 5.0 V, CL = 15 pF). It serves as a level-translating bus driver in mixed-voltage digital systems such as industrial I/O expansion and microcontroller peripheral interfacing.
For engineers reviewing the 74AHC125D,118 datasheet, 74AHC125D,118 pinout, 74AHC125D,118 application, or 74AHC125D,118 equivalent, this device is selected for its rail-to-rail input tolerance, -40 °C to +125 °C operation, Schmitt-trigger inputs, low ICC (≤40 μA at VCC = 5.5 V), and SO14 package compatibility with legacy PCB footprints.
Technical Context
The 74AHC125D,118 implements four independent non-inverting buffers, each with dedicated active-low 3-state control. Its CMOS logic family ensures TTL- and CMOS-level compatibility only in AHC variant (not AHCT), with VIH = 3.85 V and VIL = 1.65 V at VCC = 5.5 V. Input clamping diodes support overvoltage tolerance without external protection.
Propagation delay (tpd) and enable/disable timing are tightly matched across channels - tpd ≤ 5.5 ns and ten/tdis ≤ 7.0 ns under 5 V/15 pF conditions. The device uses standard positive-edge logic signaling with no internal latching or clocking; all transitions are combinatorial and synchronous to input edges.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 2.0 V to 5.5 V - supports direct interface with 3.3 V and 5 V logic domains without level shifters |
| Input voltage tolerance | Up to 5.5 V - enables safe connection to higher-voltage buses while powered from lower VCC |
| Propagation delay (tpd) | 3.0 ns (typ) at VCC = 5.0 V, CL = 15 pF - ensures minimal signal skew in high-speed data paths |
| Output drive strength | ±8.0 mA at VCC = 4.5 V - sufficient to drive 50 pF loads or multiple CMOS inputs |
| Operating temperature | -40 °C to +125 °C - qualified for extended industrial and under-hood applications |
| Input hysteresis | Schmitt-trigger action on all inputs - rejects noise on slow-rising or noisy control lines |
| Static supply current | ≤40 μA at VCC = 5.5 V - enables low-power standby in battery-backed systems |
Pinout & Package
74AHC125D,118 is housed in a plastic small outline package (SO14), SOT108-1, with 14 leads and 3.9 mm body width. Pin 1 is marked by a notch or index area; the package is RoHS-compliant and lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | 1OE, 2OE, 3OE, 4OE | Active-low 3-state enable inputs - drive corresponding Y outputs to high-impedance when HIGH |
| 2, 5, 9, 12 | 1A, 2A, 3A, 4A | Buffer input terminals - accept overvoltage-tolerant signals up to 5.5 V regardless of VCC |
| 3, 6, 8, 11 | 1Y, 2Y, 3Y, 4Y | Non-inverting buffered outputs - provide rail-to-rail CMOS-compatible drive with ±8 mA capability |
| 7 | GND | Ground reference (0 V) - must be connected to system ground plane for noise immunity and ESD path |
| 14 | VCC | Positive supply terminal - decoupling capacitor (100 nF) required within 5 mm for stable switching |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail input tolerance | Inputs withstand 5.5 V regardless of VCC (2.0–5.5 V), enabling mixed-voltage translation without external components |
| Low dynamic power | CPD = 10 pF - minimizes switching power (PD = CPD × VCC² × fi × N) in high-frequency bus applications |
| High noise immunity | Input hysteresis ≥0.5 V at VCC = 5 V - suppresses false triggering from EMI or crosstalk on shared PCB traces |
| ESD robustness | HBM > 2000 V, CDM > 1000 V - survives handling and board assembly without special ESD precautions |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level A - prevents destructive latch-up during transient overvoltage events |
Applications
| Industrial PLC I/O Expansion | Microcontroller Peripheral Bus Isolation |
|---|---|
Use Scenario: Isolating 3.3 V MCU GPIOs from 5 V sensor/actuator buses in programmable logic controllers. IC Role / Device Role / Timing Role: Bidirectional level-shifting buffer with 3-state control for time-multiplexed address/data bus sharing. Use Value: Eliminates need for discrete level shifters; overvoltage-tolerant inputs prevent damage during hot-plug or fault conditions. |
Use Scenario: Driving multiple SPI peripherals from a single microcontroller port while preventing signal contention. IC Role / Device Role / Timing Role: Quad 3-state line driver enabling selective peripheral activation via OE pins synchronized to chip-select timing. Use Value: Reduces PCB trace count and routing complexity; matched propagation delays ensure deterministic setup/hold margins. |
| Automotive Body Control Module | Test Equipment Signal Conditioning |
Use Scenario: Interfacing low-voltage CAN controller logic with 5 V analog multiplexer control lines in body electronics. IC Role / Device Role / Timing Role: Voltage-tolerant buffer isolating sensitive MCU pins from noisy 12 V-derived 5 V rails. Use Value: Operates reliably across full automotive temperature range (-40 °C to +125 °C); Schmitt inputs reject ignition noise. |
Use Scenario: Conditioning digital stimulus signals in automated test equipment before applying to DUT inputs. IC Role / Device Role / Timing Role: Low-skew, high-drive buffer ensuring clean edge integrity into capacitive probe loads. Use Value: 3.0 ns propagation delay and <100 ps channel-to-channel skew preserve signal fidelity at >100 MHz test frequencies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT125D,118 | TTL-compatible inputs (VIH = 2.0 V, VIL = 0.8 V); identical pinout and timing | Better suited for legacy 5 V TTL systems where AHC's higher VIH may cause marginal recognition | Select when interfacing with older 5 V TTL logic families; not recommended for pure CMOS or mixed 3.3/5 V systems requiring overvoltage tolerance |
| SN74LVC125APWR | Lower VCC range (1.65–3.6 V); LVTTL input thresholds; 32 mA drive; different pinout (TSSOP-14) | Optimized for 3.3 V-only systems; incompatible with 5 V inputs or 5 V supply | Choose only for 3.3 V domain designs requiring higher drive; requires PCB redesign due to non-pin-compatible layout |
Compared with 74AHCT125D,118, the 74AHC125D,118 provides superior input voltage margin and noise immunity but requires higher VIH; versus SN74LVC125APWR, it supports wider supply range and overvoltage safety at the cost of lower drive strength and no 1.8 V operation.
Availability
74AHC125D,118 is available at Aetrix Electronics and suitable for industrial automation, test equipment, and automotive body control applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AHC125D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for industrial, automotive, and computing markets.
The 74AHC125D,118 belongs to Nexperia's AHC logic family, engineered for robust mixed-voltage interoperability, low static power, and extended temperature operation in demanding embedded control environments.
FAQ
Can 74AHC125D,118 operate with VCC = 3.3 V while accepting 5 V inputs?
Yes. Its inputs are overvoltage tolerant up to 5.5 V regardless of VCC, allowing safe interface between 3.3 V-powered logic and 5 V buses. This eliminates external clamping diodes or level translators in mixed-supply systems, provided output loads remain within 3.3 V domain specifications.
What is the maximum capacitive load the outputs can drive reliably?
The outputs are characterized up to 50 pF (per Table 7), with tpd ≤ 7.5 ns and tdis ≤ 9.5 ns at VCC = 5.0 V. Driving >50 pF increases propagation delay nonlinearly and may cause ringing; for >100 pF loads, series termination or buffer staging is recommended to maintain signal integrity.
Does 74AHC125D,118 require external pull-up or pull-down resistors on OE pins?
No. OE pins have no internal pull resistors and must be actively driven LOW to enable outputs or HIGH to disable them. Leaving OE floating risks undefined output states and increased ICC; use MCU GPIOs or dedicated logic to control OE with defined voltage levels.
How does thermal performance differ between SO14 and QFN variants of this device?
The SO14 package (SOT108-1) has Ptot = 500 mW at +125 °C with 10.1 mW/K derating above 100 °C, while DHXQFN14 (SOT8014-1) is rated at 250 mW with 8.7 mW/K derating above 121 °C. SO14 offers higher absolute power handling; QFN provides better thermal resistance in space-constrained layouts.
74AHC125D,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74AHC125D,118 FAQ
1.How can I place an order for 74AHC125D,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHC125D,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHC125D,118 reliable?
The price and inventory of 74AHC125D,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHC125D,118 is usually 5 days.
3.What payment methods are accepted for 74AHC125D,118?
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4.How is shipping managed for 74AHC125D,118?
74AHC125D,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AHC125D,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHC125D,118?
For technical support, including 74AHC125D,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHC125D,118 requirements.
6.How does Aetrix verify that 74AHC125D,118 is sourced from the original manufacturer or authorized distributors?
All 74AHC125D,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHC125D,118 meets industry standards.
7.What is the process for return or replacement of 74AHC125D,118?
All 74AHC125D,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHC125D,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHC125D,118 part is unused and in its original packaging.
Return procedure for 74AHC125D,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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