Nexperia USA Inc. 74AHC125D-Q100,118
- Part No.:
- 74AHC125D-Q100,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74AHC125D-Q100,118.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 14SO
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AHC125D-Q100,118 from Nexperia is an automotive-qualified quad buffer/line driver with 3-state outputs, designed for voltage-level translation in mixed-voltage systems. It operates from 2.0 V to 5.5 V, features overvoltage-tolerant inputs up to 5.5 V, supports -40 °C to +125 °C ambient range, and delivers propagation delay as low as 3.0 ns (VCC = 5.0 V, CL = 15 pF). It is used in automotive body control modules for isolating and driving multiple CAN/LIN interface signal lines.
For engineers reviewing the 74AHC125D-Q100,118 datasheet, 74AHC125D-Q100,118 pinout, 74AHC125D-Q100,118 application, or 74AHC125D-Q100,118 equivalent, this page provides verified functional identity, AEC-Q100 Grade 1 qualification status, SO14 package mapping, confirmed 3-state enable timing (ten ≤ 7.0 ns), and direct substitution guidance against industry-standard logic buffers.
Technical Context
This device implements four independent non-inverting buffers, each with active-low 3-state output enable (nOE) controlling high-impedance output states. Input logic thresholds are CMOS-compatible (VIH ≥ 3.85 V at VCC = 5.5 V), enabling interoperability with 3.3 V and 5 V logic domains without level shifters.
All inputs include Schmitt-trigger action for noise immunity, and the device exhibits balanced tPLH/tPHL propagation delays (≤ 5.5 ns typical at 5 V/15 pF). Output drive strength is ±8 mA at VCC = 4.5 V, with VOL ≤ 0.36 V and VOH ≥ 3.94 V under load - ensuring robust TTL- and CMOS-compatible signaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - enables single-supply operation across 3.3 V and 5 V systems without external regulators. |
| Operating Temperature | -40 °C to +125 °C - qualified per AEC-Q100 Grade 1 for under-hood automotive use. |
| Propagation Delay (tpd) | 3.0 ns (typ, VCC = 5.0 V, CL = 15 pF) - supports high-speed bus buffering up to ~150 MHz data rates. |
| Output Drive Strength | ±8 mA (VOH/VOL guaranteed at VCC = 4.5 V) - sufficient to drive 50 pF loads with <10 ns edge integrity. |
| Input Overvoltage Tolerance | Up to 5.5 V regardless of VCC - allows safe interfacing with higher-voltage peripherals in mixed-rail designs. |
| 3-State Enable Time (ten) | ≤ 7.0 ns (VCC = 5.0 V, CL = 50 pF) - ensures fast bus turnaround in time-critical multiplexed architectures. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - meets automotive ESD robustness requirements per JS-001/JS-002. |
Pinout & Package
74AHC125D-Q100,118 is supplied in a plastic small outline package (SO14), SOT108-1, with 14 leads and 3.9 mm body width. The package includes standard gull-wing leads compatible with automated PCB assembly and reflow.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (active-low output enable) | Independent control per buffer; LOW enables output, HIGH forces high-impedance state. |
| 2, 5, 9, 12 | nA (data input) | CMOS-level input with Schmitt-trigger hysteresis; tolerant to 5.5 V regardless of VCC. |
| 3, 6, 8, 11 | nY (data output) | Non-inverting buffered output; 3-state capable with rail-to-rail swing and ±8 mA drive. |
| 7 | GND | Reference ground for all I/O and supply terminals; decoupling capacitor placement critical for noise immunity. |
| 14 | VCC | Primary power supply input; must be bypassed locally with 100 nF ceramic capacitor near pin 14. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for automotive use from -40 °C to +125 °C ambient, including thermal cycling and HTOL stress. |
| Overvoltage-tolerant inputs | Accepts 0–5.5 V input signals irrespective of VCC setting - eliminates need for external level translators. |
| Low dynamic power dissipation | CPD = 10 pF - enables sub-1 mW operation at 1 MHz with 5 V supply and 4 switching inputs. |
| Schmitt-trigger inputs | Hysteresis ≥ 0.3 V (typ) - rejects noise on slow-rising or noisy control lines such as wake-up signals. |
| DHVQFN/SO14/TSSOP package options | SO14 (SOT108-1) variant offers proven reliability and legacy board compatibility for automotive ECUs. |
Applications
| Automotive Body Control Module | Instrument Cluster Signal Isolation |
|---|---|
|
Use Scenario: Driving multiple LIN transceiver enable lines from a single microcontroller GPIO bank while maintaining electrical isolation between subsystems. IC Role / Device Role / Timing Role: Quad buffer provides independent 3-state control per LIN channel, enabling time-multiplexed bus arbitration without crosstalk. Use Value: Eliminates discrete MOSFET switches and pull-up networks, reducing BOM count by 4× and PCB area by >30% versus discrete solutions. |
Use Scenario: Buffering analog sensor signals (e.g., fuel level, temperature) before ADC sampling in a digital instrument cluster. IC Role / Device Role / Timing Role: Acts as input signal conditioner with Schmitt-trigger inputs to reject EMI-induced glitches on long harness runs. Use Value: Prevents false ADC triggers caused by <100 ns noise spikes - improves system reliability without firmware debouncing overhead. |
| ADAS Camera Power Sequencing | Infotainment System Bus Expansion |
|
Use Scenario: Enabling/disabling power rails for camera image sensors and ISP processors during sleep/wake transitions. IC Role / Device Role / Timing Role: 3-state outputs control enable pins of multiple LDOs; fast ten/tdis ensures synchronized power sequencing within 10 ns tolerance. Use Value: Meets ISO 26262 ASIL-B timing constraints for power domain coordination without FPGA or CPLD involvement. |
Use Scenario: Expanding I²C or SPI bus segments across multiple PCB zones in head unit designs with space-constrained layouts. IC Role / Device Role / Timing Role: Buffers clock and data lines to maintain signal integrity across >10 cm trace lengths with minimal skew. Use Value: Enables reliable 400 kHz I²C operation across split-board interfaces where direct routing causes >20% rise-time degradation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT125D-Q100 | TTL-compatible input thresholds (VIH = 2.0 V min), slightly higher ICC (max 40 μA vs. 20 μA at 5.5 V) | Better suited for legacy 5 V microcontrollers with TTL output drivers; less ideal for 3.3 V-only SoCs | Select when interfacing with older MCU families (e.g., PIC18F, ATmega128) requiring TTL-level recognition. |
| SN74LVC125APWR | Lower VCC range (1.65–3.6 V), no AEC-Q100 qualification, smaller TSSOP-14 package (SOT402-1) | Limited to cabin electronics (e.g., HVAC controls); not rated for under-hood temperature extremes | Choose only for cost-sensitive, non-safety-critical interior modules where AEC-Q100 is not mandated. |
Compared with 74AHCT125D-Q100, the 74AHC125D-Q100 offers superior noise immunity and wider voltage compatibility but requires CMOS-level inputs; versus SN74LVC125APWR, it trades package size and cost for automotive-grade reliability and extended temperature support.
Availability
74AHC125D-Q100,118 is available at Aetrix Electronics and suitable for automotive body control modules, instrument cluster signal conditioning, ADAS camera power sequencing, and infotainment bus expansion requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AHC125D-Q100,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for automotive, industrial, and mobile applications - with emphasis on reliability, efficiency, and AEC-Q100 compliance.
The 74AHC125-Q100 series belongs to Nexperia's automotive logic portfolio, engineered specifically for robust signal buffering and voltage translation in harsh-temperature vehicle subsystems where failure is not an option.
FAQ
What is the maximum allowable input voltage on the A pins when VCC = 3.3 V?
The input pins are overvoltage tolerant up to 5.5 V regardless of VCC level. When VCC = 3.3 V, inputs may safely accept signals from 0 V to 5.5 V without damage or latch-up - a key enabler for mixed-voltage signal routing in automotive gateways.
Does 74AHC125D-Q100,118 support hot insertion or live bus connection?
No. While the device has high-impedance 3-state outputs, it lacks true hot-swap protection circuitry such as slew-rate limiting or back-drive current blocking. Connecting or disconnecting while powered may cause transient currents exceeding ±20 mA clamping limits, risking long-term reliability degradation.
Can the 74AHC125D-Q100,118 drive a 50 Ω transmission line directly?
No. Its output drive capability (±8 mA) is insufficient to properly terminate a 50 Ω line at 3.3 V or 5 V. For controlled-impedance traces, use a dedicated line driver (e.g., SN65LVDS1) or add series termination resistors (e.g., 33 Ω) to match characteristic impedance while preserving logic levels.
Is there a recommended PCB layout practice for minimizing ground bounce in high-speed switching?
Yes. Place a 100 nF X7R ceramic decoupling capacitor between VCC (pin 14) and GND (pin 7) with trace length < 3 mm. Use a solid ground plane beneath the SO14 footprint, avoid splits under the device, and route nOE/nA/nY traces away from noisy power or clock nets to maintain >20 dB noise margin.
74AHC125D-Q100,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74AHC125D-Q100,118 FAQ
1.How can I place an order for 74AHC125D-Q100,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHC125D-Q100,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHC125D-Q100,118 reliable?
The price and inventory of 74AHC125D-Q100,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHC125D-Q100,118 is usually 5 days.
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Once your 74AHC125D-Q100,118 order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for 74AHC125D-Q100,118?
For technical support, including 74AHC125D-Q100,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHC125D-Q100,118 requirements.
6.How does Aetrix verify that 74AHC125D-Q100,118 is sourced from the original manufacturer or authorized distributors?
All 74AHC125D-Q100,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHC125D-Q100,118 meets industry standards.
7.What is the process for return or replacement of 74AHC125D-Q100,118?
All 74AHC125D-Q100,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHC125D-Q100,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHC125D-Q100,118 part is unused and in its original packaging.
Return procedure for 74AHC125D-Q100,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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