Nexperia USA Inc. 74AHC126PW-Q100,11
- Part No.:
- 74AHC126PW-Q100,11
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74AHC126PW-Q100,11.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,858
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AHC126PW-Q100 from Nexperia is an automotive-qualified quad buffer/line driver with 3-state outputs, CMOS-level input compatibility, overvoltage-tolerant inputs (up to 7.0 V), and operation across -40 °C to +125 °C. It features balanced propagation delays (as low as 3.3 ns at VCC = 5.5 V, CL = 15 pF), Schmitt-trigger inputs, and TTL-compatible variants (74AHCT126PW-Q100) for mixed-voltage bus interfacing in engine control units and ADAS domain controllers.
For engineers reviewing the 74AHC126PW-Q100 datasheet, 74AHC126PW-Q100 pinout, 74AHC126PW-Q100 application, or 74AHC126PW-Q100 equivalent, key selection criteria include 3-state enable timing (tdis ≤ 9.5 ns), output drive capability (±8 mA at VCC = 4.5 V), AEC-Q100 Grade 1 qualification, and TSSOP14 package suitability for high-density automotive PCB layouts.
Technical Context
This device implements four independent non-inverting buffers, each with a dedicated active-HIGH output enable (nOE) controlling high-impedance state entry/exit. Input overvoltage tolerance enables safe level translation between 3.3 V logic domains and 5 V buses without external clamping.
Schmitt-trigger inputs provide noise immunity on slow-rising signals, while balanced tPLH/tPHL ensures minimal duty-cycle distortion in clock distribution paths. The 3-state architecture supports bidirectional bus sharing in CAN/LIN transceiver interface logic and sensor data multiplexing circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - Supports dual-rail operation in 3.3 V and 5 V automotive subsystems |
| Propagation Delay (tpd) | 3.3 ns (typ) at VCC = 5.5 V, CL = 15 pF - Enables reliable signal routing in sub-10 ns timing-critical paths |
| Output Drive Strength | ±8 mA at VOH/VOL - Sustains 50 Ω transmission line termination and drives ≥10 LSTTL loads |
| Input Voltage Tolerance | -0.5 V to +7.0 V - Allows direct connection to 5 V buses without level shifters when powered from 3.3 V |
| Enable/Disable Time | ten = 4.7 ns, tdis = 6.7 ns (typ) at VCC = 5.5 V - Minimizes bus contention windows during hot-swap or power sequencing |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - Meets stringent AEC-Q100 stress requirements for under-hood electronics |
| Operating Temperature | -40 °C to +125 °C - Qualified for engine compartment and powertrain control module deployment |
Pinout & Package
TSSOP14 plastic thin shrink small outline package (SOT402-1); 14 leads; body width 4.4 mm; 0.65 mm pitch; exposed pad not electrically connected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (output enable) | Active-HIGH control per buffer - enables/disables corresponding output independently |
| 2, 5, 9, 12 | nA (data input) | CMOS-level input with Schmitt-trigger action - rejects noise on long harness traces |
| 3, 6, 8, 11 | nY (data output) | 3-state CMOS output - enters high-Z when nOE = LOW, preventing bus conflicts |
| 7 | GND | Ground reference - must be low-inductance connection to minimize switching noise coupling |
| 14 | VCC | Power supply - decoupling capacitor (100 nF) required within 5 mm of pin for stable operation |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for automotive use from -40 °C to +125 °C ambient - eliminates requalification effort for Tier 1 suppliers |
| Overvoltage-tolerant inputs | Accepts up to 7.0 V regardless of VCC - enables direct interfacing with 5 V sensors while powered from 3.3 V MCU rails |
| Schmitt-trigger inputs | Hysteresis ≥ 0.3 V at VCC = 5 V - suppresses EMI-induced glitches on CAN/LIN bus lines and switch inputs |
| Balanced propagation delays | tPLH and tPHL match within 0.3 ns - preserves signal integrity in clock fanout and data strobe applications |
| TSSOP14 with side-wettable flanks | SOT402-1 package - enables automated optical inspection (AOI) of solder joints for zero-defect automotive manufacturing |
Applications
| Engine Control Unit (ECU) I/O Expansion | ADAS Camera Interface Multiplexer |
|---|---|
|
Use Scenario: Expanding GPIO count of a 3.3 V microcontroller to drive multiple 5 V solenoid drivers and analog sensor references. IC Role / Device Role / Timing Role: Level-translating buffer enabling bidirectional signal routing between MCU and higher-voltage peripherals. Use Value: Eliminates need for discrete level shifters; overvoltage tolerance prevents latch-up during load dump events. |
Use Scenario: Selecting between two MIPI CSI-2 camera streams using a single serializer IC with shared control lines. IC Role / Device Role / Timing Role: 3-state bus switch isolating camera configuration registers during channel switching. Use Value: Prevents register corruption via bus contention; <9.5 ns disable time ensures glitch-free stream handover. |
| Body Control Module (BCM) LIN Bus Transceiver Interface | Infotainment System Display Backlight Driver Enable Logic |
|
Use Scenario: Isolating LIN transceiver TX/RX lines from MCU pins during sleep mode to reduce quiescent current. IC Role / Device Role / Timing Role: Controlled buffer gating LIN communication path based on wake-up interrupt status. Use Value: Reduces system standby current by >15 μA per channel; Schmitt inputs reject noise from vehicle battery ripple. |
Use Scenario: Enabling/disabling PWM-controlled LED backlight drivers synchronized to display frame start pulses. IC Role / Device Role / Timing Role: Timing-critical enable gate ensuring backlight activation occurs only after panel initialization completes. Use Value: Prevents visible flash artifacts; 3.3 ns propagation delay aligns enable edge within ±2 ns of frame sync signal. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT126PW-Q100 | TTL-level inputs (VIH = 2.0 V min), identical pinout and timing | Better compatibility with legacy 5 V TTL logic families; slightly higher ICC at VCC = 5 V | Select when interfacing with older 5 V microcontrollers or discrete transistor logic |
| SN74LVC126APWREP | Lower VCC range (1.65–3.6 V), LVCMOS inputs, no overvoltage tolerance | Optimized for 1.8 V/3.3 V-only systems; unsuitable for mixed-voltage translation | Choose only for pure low-voltage designs where overvoltage protection is unnecessary |
Compared with 74AHCT126PW-Q100, the AHC variant offers superior noise margin in noisy automotive environments due to higher VIH; versus SN74LVC126APWREP, it trades lower power for essential 7 V input tolerance required in under-hood applications.
Availability
74AHC126PW-Q100 is available at Aetrix Electronics and suitable for engine control units, ADAS camera modules, and body control modules requiring stable component supply across extended temperature ranges and AEC-Q100 compliance.
Supply support for 74AHC126PW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile applications.
The 74AHC-Q100 series delivers AEC-Q100 qualified logic devices engineered specifically for harsh automotive environments, emphasizing robustness, thermal stability, and long-term supply assurance.
FAQ
Is the 74AHC126PW-Q100 pin-compatible with standard 74HC126 packages?
Yes - the TSSOP14 (SOT402-1) footprint matches JEDEC MO-153 standards and is mechanically and electrically compatible with industry-standard 74HC126 TSSOP packages. Pin numbering, function mapping, and thermal pad layout are identical, enabling drop-in replacement in existing designs without PCB revision.
What is the maximum capacitive load this device can drive while maintaining specified timing?
The datasheet specifies timing parameters up to 50 pF load capacitance. At CL = 50 pF and VCC = 5.5 V, tpd remains ≤ 7.5 ns and tdis ≤ 9.5 ns. Driving loads beyond 50 pF increases propagation delay nonlinearly and may violate setup/hold margins in high-speed interfaces like SPI or parallel sensor buses.
Can the 74AHC126PW-Q100 be used with a 2.5 V supply voltage?
No - the minimum recommended VCC is 2.0 V, but static characteristics (VIH, VOL) are only guaranteed down to 2.0 V at -40 °C to +125 °C. At 2.5 V, VOH drops below 2.0 V (min) and VOL rises above 0.55 V (max), risking logic-level misinterpretation in downstream 3.3 V receivers; 3.0 V or higher is strongly recommended.
Does the exposed thermal pad on the TSSOP14 package require electrical connection?
No - the exposed pad in SOT402-1 is a mechanical thermal enhancement feature only. Per Nexperia documentation, it has no electrical function and may remain floating or be connected to GND solely for thermal conduction; no electrical tie is required or recommended for signal integrity.
74AHC126PW-Q100,11 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHC
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
74AHC126PW-Q100,11 FAQ
1.How can I place an order for 74AHC126PW-Q100,11 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHC126PW-Q100,11 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHC126PW-Q100,11 reliable?
The price and inventory of 74AHC126PW-Q100,11 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHC126PW-Q100,11 is usually 5 days.
3.What payment methods are accepted for 74AHC126PW-Q100,11?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AHC126PW-Q100,11 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AHC126PW-Q100,11?
74AHC126PW-Q100,11 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AHC126PW-Q100,11 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHC126PW-Q100,11?
For technical support, including 74AHC126PW-Q100,11 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHC126PW-Q100,11 requirements.
6.How does Aetrix verify that 74AHC126PW-Q100,11 is sourced from the original manufacturer or authorized distributors?
All 74AHC126PW-Q100,11 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHC126PW-Q100,11 meets industry standards.
7.What is the process for return or replacement of 74AHC126PW-Q100,11?
All 74AHC126PW-Q100,11 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHC126PW-Q100,11, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHC126PW-Q100,11 part is unused and in its original packaging.
Return procedure for 74AHC126PW-Q100,11:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AHC126PW-Q100,11 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

