Nexperia USA Inc. 74AHC1G125GV-Q100H
- Part No.:
- 74AHC1G125GV-Q100H
- Manufacturer:
- Nexperia USA Inc.
- Package:
- SC-74A, SOT-753
- Datasheet:
-
74AHC1G125GV-Q100H.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SC74A
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AHC1G125GV-Q100 from Nexperia is a single-channel 3-state bus buffer/line driver with overvoltage-tolerant inputs (up to 5.5 V), CMOS-level input compatibility, and AEC-Q100 Grade 1 qualification for automotive use. It operates from 2.0 V to 5.5 V supply, delivers ≤7.0 ns propagation delay at 5 V/50 pF, and features symmetrical output impedance for clean signal integrity in bidirectional bus interfaces.
For engineers reviewing the 74AHC1G125GV-Q100 datasheet, 74AHC1G125GV-Q100 pinout, 74AHC1G125GV-Q100 application, or 74AHC1G125GV-Q100 equivalent, this device serves as a voltage-translation-capable unidirectional buffer in CAN/LIN subsystems, sensor interface multiplexing, and automotive body control modules where rail-to-rail input tolerance and low-power 3-state control are required.
Technical Context
This device implements a single non-inverting buffer with active-low 3-state enable (OE), supporting mixed-voltage system interfacing via overvoltage-tolerant inputs that accept up to 5.5 V regardless of VCC (2.0–5.5 V). Its logic function follows standard IEEE/IEC 60617 truth table behavior: output Y equals input A when OE = LOW; Y is high-impedance when OE = HIGH.
The SC-74A (SOT753) package supports thermal performance up to +125 °C ambient, with total power dissipation derating at 3.8 mW/K above 85 °C. Input leakage remains ≤2.0 μA across temperature, and output drive capability is ±8 mA at VCC = 4.5 V, enabling direct connection to standard CMOS loads without external termination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - Enables operation across 3.3 V and 5 V domains without level shifters. |
| Input Voltage Tolerance | Up to 5.5 V - Allows safe interfacing with higher-voltage peripherals even when VCC = 2.0 V. |
| Propagation Delay (tpd) | ≤5.5 ns at VCC = 5.0 V, CL = 15 pF - Supports >100 MHz data rates in short-bus applications. |
| Output Drive Strength | ±8.0 mA at VOH/VOL limits - Sufficient to drive 15 pF load with <0.55 V VOL at 4.0 mA sink. |
| Operating Temperature | −40 °C to +125 °C - Qualified per AEC-Q100 Grade 1 for under-hood automotive environments. |
| ESD Protection | HBM >2000 V, CDM >1000 V - Robust handling during PCB assembly and in-vehicle ESD events. |
| Quiescent Supply Current | ≤40 μA at VCC = 5.5 V - Enables ultra-low static power in always-on vehicle subsystems. |
Pinout & Package
74AHC1G125GV-Q100 uses the SC-74A (SOT753) surface-mount package: plastic, 5-terminal, 1.25 mm body width, 0.95 mm lead pitch, and 1.1 × 0.9 mm footprint. Pin 1 (OE) is located at the lower-left corner beneath the marking "A25".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Active-low output enable | Drives Y to high-impedance when HIGH; enables buffer pass-through when LOW. |
| 2 (A) | Data input | CMOS-compatible input accepting 0–5.5 V; no internal pull-up/down. |
| 3 (GND) | Ground reference | 0 V return path for all internal circuitry and output current sinking. |
| 4 (Y) | Buffered output | Non-inverted, 3-state output with symmetrical rise/fall times and ±8 mA drive. |
| 5 (VCC) | Positive supply | Primary power rail; powers internal logic and output stage; tolerant to 7.0 V transient. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for −40 °C to +125 °C operation in automotive powertrain and chassis systems. |
| Overvoltage-tolerant inputs | Accepts 0–5.5 V signals independent of VCC, enabling seamless 3.3 V ↔ 5 V translation. |
| Low dynamic power dissipation | CPD = 9 pF - Minimizes switching power in high-frequency bus applications. |
| Symmetrical output impedance | Matched pull-up/pull-down strength ensures consistent edge rates and reduced overshoot. |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level A - Prevents destructive latch-up during transients. |
Applications
| Automotive Body Control Module (BCM) | Infotainment System I/O Expansion |
|---|---|
Use Scenario: Isolating microcontroller GPIOs from high-noise door lock actuators and window motor drivers. IC Role / Device Role / Timing Role: Unidirectional 3-state buffer enabling software-controlled isolation of MCU pins from noisy loads. Use Value: Prevents backfeed and noise coupling into MCU while maintaining fast response (<7 ns) for real-time actuator control. |
Use Scenario: Expanding I²C or SPI peripheral count on head unit SoC with limited native GPIOs. IC Role / Device Role / Timing Role: Bus buffer isolating secondary I²C slave devices from main controller during hot-swap or fault conditions. Use Value: Enables hot-plug-safe peripheral addition without disrupting primary bus timing or causing address conflicts. |
| Advanced Driver Assistance Systems (ADAS) Sensor Hub | Automotive Gateway Controller Interface |
Use Scenario: Multiplexing analog sensor outputs (e.g., radar proximity, ambient light) onto shared ADC input lines. IC Role / Device Role / Timing Role: Signal routing buffer with precise enable timing to prevent channel crosstalk during sampling windows. Use Value: Ensures <10 ns enable/disable skew between sensors, preserving time-of-flight measurement accuracy. |
Use Scenario: Level-shifting and buffering LIN bus signals between gateway MCU (3.3 V) and legacy 12 V LIN transceivers. IC Role / Device Role / Timing Role: Voltage-tolerant line driver translating logic levels while maintaining LIN physical layer timing compliance. Use Value: Eliminates need for discrete level-shifters; maintains <15 ns propagation delay margin for LIN 19.2 kbps timing budget. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT1G125GV-Q100 | TTL-compatible inputs (VIH = 2.0 V min), otherwise identical pinout, timing, and packaging. | Better suited for legacy 5 V TTL logic interfacing; less suitable for pure CMOS 3.3 V systems with marginal noise margins. | Select when interfacing with older 5 V microcontrollers or discrete TTL gates requiring 2.0 V VIH threshold. |
| SN74LVC1G125DBVR | Lower VCC range (1.65–5.5 V), higher ICC (max 10 μA vs. 40 μA), same SC-70-5 package but not AEC-Q100 qualified. | Not automotive-qualified; intended for industrial/commercial use only; lacks AEC-Q100 test documentation. | Select for cost-sensitive non-automotive designs requiring wider low-voltage support down to 1.65 V. |
Compared with 74AHCT1G125GV-Q100, the AHC variant offers tighter VIH/VIL thresholds for robust CMOS noise immunity, while SN74LVC1G125DBVR trades automotive qualification for broader low-voltage operation-making the 74AHC1G125GV-Q100 optimal for safety-critical 3.3 V/5 V mixed-signal automotive nodes.
Availability
74AHC1G125GV-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, ADAS sensor hubs, infotainment I/O expansion, and gateway controller interfaces requiring stable component supply across extended temperature ranges and AEC-Q100 compliance.
Supply support for 74AHC1G125GV-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, with leadership in automotive-grade components and advanced packaging.
This device belongs to Nexperia's AHC-Q100 automotive logic family, engineered specifically for robust signal buffering in harsh-temperature vehicle subsystems where voltage translation, low power, and AEC-Q100 reliability are mandatory.
FAQ
Is 74AHC1G125GV-Q100 pin-compatible with 74AHCT1G125GV-Q100?
Yes - both share identical SC-74A (SOT753) pinout, package dimensions, and terminal assignments. The only functional difference is input threshold: AHC uses CMOS-compatible VIH (≥70% VCC), while AHCT uses TTL-compatible VIH (≥2.0 V). No PCB redesign is needed for substitution.
What is the maximum capacitive load this buffer can drive reliably?
The device is characterized up to 50 pF load capacitance with guaranteed timing (tpd ≤7.5 ns at VCC = 5 V). Driving >50 pF may increase propagation delay and reduce edge rate but will not damage the part; for loads >75 pF, consider adding series termination or using a higher-drive buffer.
Does this part support hot insertion or live bus connection?
Yes - its overvoltage-tolerant inputs (to 5.5 V) and high-impedance OFF-state (IOZ ≤10 μA) allow safe connection to powered buses. However, OE must be held LOW before VCC ramp-up to avoid undefined output states during power sequencing.
How does the 3-state disable timing affect system-level bus arbitration?
tdis (disable time) is ≤9.5 ns at VCC = 5 V/CL = 50 pF, ensuring rapid bus release. This allows tight arbitration windows in multi-master systems - e.g., in LIN cluster networks, it guarantees <10 ns bus turnaround between master and slave transmissions without collision.
74AHC1G125GV-Q100H Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHC
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-74A
74AHC1G125GV-Q100H FAQ
1.How can I place an order for 74AHC1G125GV-Q100H through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHC1G125GV-Q100H on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHC1G125GV-Q100H reliable?
The price and inventory of 74AHC1G125GV-Q100H are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHC1G125GV-Q100H is usually 5 days.
3.What payment methods are accepted for 74AHC1G125GV-Q100H?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AHC1G125GV-Q100H transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AHC1G125GV-Q100H?
74AHC1G125GV-Q100H orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AHC1G125GV-Q100H order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHC1G125GV-Q100H?
For technical support, including 74AHC1G125GV-Q100H datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHC1G125GV-Q100H requirements.
6.How does Aetrix verify that 74AHC1G125GV-Q100H is sourced from the original manufacturer or authorized distributors?
All 74AHC1G125GV-Q100H products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHC1G125GV-Q100H meets industry standards.
7.What is the process for return or replacement of 74AHC1G125GV-Q100H?
All 74AHC1G125GV-Q100H units undergo pre-shipment inspection (PSI). If there is an issue with 74AHC1G125GV-Q100H, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHC1G125GV-Q100H part is unused and in its original packaging.
Return procedure for 74AHC1G125GV-Q100H:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AHC1G125GV-Q100H Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

