Nexperia USA Inc. 74AHC1G126GV,125
- Part No.:
- 74AHC1G126GV,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- SC-74A, SOT-753
- Datasheet:
-
74AHC1G126GV,125.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SC74A
- Quantity:
- Payment:

- Shipping:

Inventory:1,715
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Product details
Overview
74AHC1G126GV,125 from Nexperia is a single CMOS bus buffer/line driver with 3-state output, overvoltage-tolerant inputs (up to 5.5 V), wide supply range (2.0–5.5 V), and operation from –40 °C to +125 °C. It functions as a level-translating unidirectional driver in mixed-voltage I/O interfaces, such as between 3.3 V microcontrollers and 5 V peripherals.
For engineers reviewing the 74AHC1G126GV,125 datasheet, 74AHC1G126GV,125 pinout, 74AHC1G126GV,125 application, or 74AHC1G126GV,125 equivalent, this device is selected for low-power, high-noise-immunity bidirectional bus control where input voltage translation and fast enable/disable timing are critical - especially in industrial PLC I/O modules, sensor interface hubs, and embedded system backplanes.
Technical Context
This logic buffer implements a non-inverting 3-state output controlled by an active-low enable input (OE). Its overvoltage-tolerant inputs allow direct connection to 5.5 V signals while powered from as low as 2.0 V, enabling seamless voltage-level translation without external resistors or translators.
It features symmetrical output impedance and balanced propagation delays (tpd ≤ 7.0 ns at VCC = 4.5–5.5 V, CL = 50 pF), with enable/disable times (ten/tdis) tightly matched (≤ 9.5 ns max at same conditions), supporting reliable timing in synchronous bus arbitration and hot-swap signal routing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - supports dual-rail systems and brown-out tolerant operation across 3.3 V and 5 V domains. |
| Input Voltage Tolerance | Up to 5.5 V independent of VCC - enables safe interfacing with higher-voltage buses without clamping diodes. |
| Propagation Delay (tpd) | ≤ 7.0 ns (VCC = 4.5–5.5 V, CL = 50 pF) - ensures sub-10 ns timing margin for 50 MHz bus handshaking. |
| Enable Time (ten) | ≤ 9.5 ns (VCC = 4.5–5.5 V, CL = 50 pF) - allows rapid bus turnaround in time-critical multiplexed data paths. |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive ECUs, industrial motor drives, and outdoor telecom equipment. |
| Output Drive Strength | ±8 mA (VOH/VOL @ VCC = 4.5 V) - sufficient to drive 15 pF loads across 10 cm PCB traces without termination. |
| Power Dissipation | CPD = 9 pF - enables accurate dynamic power estimation (PD = CPD × VCC² × fi) for battery-powered edge nodes. |
Pinout & Package
74AHC1G126GV,125 uses the SC-74A (SOT753) surface-mount package: plastic, 5-lead, body size 3.1 mm × 1.7 mm × 1.3 mm, with gull-wing leads and pin 1 indicator below marking "A26".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable input | Active-low control: pulls Y to high-impedance when LOW; asserts buffered A→Y path when HIGH. |
| 2 (A) | Data input | CMOS-compatible input accepting 0–5.5 V; tolerant of overshoot beyond VCC during hot-plug events. |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output current; must be low-inductance for noise immunity. |
| 4 (Y) | 3-state output | Non-inverting buffered output; sinks or sources up to 8 mA; enters high-Z state within 9.5 ns of OE deassertion. |
| 5 (VCC) | Supply voltage | Primary power rail (2.0–5.5 V); decoupling capacitor (100 nF) required within 5 mm for stable switching. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-tolerant inputs | Withstands 5.5 V regardless of VCC down to 2.0 V - eliminates need for external level shifters in mixed-voltage designs. |
| Symmetrical output impedance | Matched rise/fall drive strength ensures clean signal edges and minimal duty-cycle distortion on Y. |
| High noise immunity | Typical VIH = 3.85 V / VIL = 1.65 V at VCC = 5.5 V - provides >1.5 V noise margin against EFT and conducted transients. |
| Low static current | ICC ≤ 40 μA at VCC = 5.5 V, –40 °C to +125 °C - enables always-on monitoring circuits in energy-constrained systems. |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level A - prevents destructive latch-up during I/O fault conditions. |
Applications
| Industrial Sensor Hub | Microcontroller I/O Expansion |
|---|---|
Use Scenario: Aggregating analog sensor outputs (e.g., temperature, pressure) into a shared 3.3 V ADC bus with configurable channel isolation. IC Role / Device Role / Timing Role: Acts as a 3-state gate between sensor front-end and ADC input, enabling one-at-a-time sampling without crosstalk. Use Value: Overvoltage tolerance allows direct connection to 5 V sensor outputs; low propagation delay (<7 ns) preserves timing integrity during burst-mode acquisition. |
Use Scenario: Extending GPIO count of a 3.3 V ARM Cortex-M4 MCU to drive legacy 5 V logic peripherals (e.g., displays, EEPROMs). IC Role / Device Role / Timing Role: Serves as a unidirectional level-translating buffer, isolating MCU pins from 5 V bus loading and transient coupling. Use Value: Input tolerance to 5.5 V eliminates external pull-ups or translators; ±8 mA drive supports fan-out to three 5 V TTL loads. |
| Programmable Logic Controller (PLC) Backplane | Hot-Swappable Module Interface |
Use Scenario: Isolating field I/O modules (24 V digital inputs) from a 3.3 V FPGA-based controller via optocoupler-isolated 5 V logic rails. IC Role / Device Role / Timing Role: Buffers and gates optocoupler output signals onto the FPGA's 5 V I/O bus, synchronized to enable strobes. Use Value: 125 °C rating ensures reliability in enclosed control cabinets; fast enable/disable (<10 ns) enables deterministic scan-cycle timing. |
Use Scenario: Enabling/disabling communication lines (e.g., UART, SPI) during live insertion of daughter cards in modular test equipment. IC Role / Device Role / Timing Role: Provides controlled bus disconnection using OE to prevent signal contention during card mating/unmating. Use Value: High-Z state leakage < ±10 μA minimizes bus leakage during hot-swap; robust ESD (HBM >2 kV) protects against contact discharge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT1G126GV,125 | TTL-compatible input thresholds (VIH = 2.0 V, VIL = 0.8 V at VCC = 5 V) vs. CMOS thresholds in AHC variant. | Better suited for interfacing with legacy 5 V TTL outputs; less suitable for low-VCC (2.0–3.3 V) systems requiring precise CMOS threshold matching. | Select AHCT if driving from standard 5 V TTL sources; select AHC for mixed-supply translation or ultra-low ICC. |
| SN74LVC1G126DBVR | Wider VCC range (1.65–5.5 V); lower typical tpd (5.2 ns @ 3.3 V); LVC family offers tighter VOH/VOL specs at 3.3 V. | Preferred for 1.8 V/3.3 V-only systems; not rated for –40 °C to +125 °C (only –40 °C to +125 °C for some variants - verify specific DBVR suffix). | Choose LVC for cost-sensitive 3.3 V designs needing faster speed; retain AHC for guaranteed 125 °C operation and superior 2.0 V compatibility. |
Compared with 74AHCT1G126GV,125, the AHC version delivers lower static current and broader low-VCC compatibility, while SN74LVC1G126DBVR offers faster timing at 3.3 V but lacks full industrial temperature assurance - making 74AHC1G126GV,125 optimal for ruggedized mixed-voltage control layers.
Availability
74AHC1G126GV,125 is available at Aetrix Electronics and suitable for industrial sensor hubs, programmable logic controller backplanes, and hot-swappable module interfaces requiring stable component supply across extended temperature ranges and mixed-voltage environments.
Supply support for 74AHC1G126GV,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.
The 74AHC1G126GV,125 belongs to Nexperia's advanced AHC logic family, designed specifically for low-power, high-speed, mixed-voltage interface applications in industrial automation, automotive subsystems, and IoT edge nodes.
FAQ
Can 74AHC1G126GV,125 operate reliably at 2.0 V supply?
Yes. The device is fully specified from 2.0 V to 5.5 V, with guaranteed VIH = 1.5 V and VIL = 0.5 V at VCC = 2.0 V, and functional operation confirmed down to –40 °C. Propagation delay increases to ≤10.0 ns (CL = 50 pF), maintaining timing predictability in ultra-low-power systems.
What is the maximum capacitive load it can drive while meeting timing specs?
At VCC = 4.5–5.5 V, the datasheet guarantees tpd ≤ 7.0 ns and ten/tdis ≤ 9.5 ns for CL = 50 pF. Driving >50 pF increases delay nonlinearly; for 100 pF loads, measured tpd rises to ~11 ns. Use series termination or reduce trace length if exceeding 50 pF.
Is pin 1 orientation consistent across SOT753 packages?
Yes. Per Nexperia's SOT753 outline (Fig. 8), pin 1 is located at the lower-left corner beneath the marking "A26", with leads numbered counter-clockwise: OE (1), A (2), GND (3), Y (4), VCC (5). This matches JEDEC-standard SC-74A pinout.
Does it support hot-swap without external protection?
Its overvoltage-tolerant inputs (to 5.5 V) and high ESD robustness (HBM >2 kV, CDM >1 kV) provide baseline hot-swap resilience, but external series resistors (10–33 Ω) and local TVS diodes are recommended for sustained 24 V field wiring exposure or frequent insertion cycles.
74AHC1G126GV,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHC
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-74A
74AHC1G126GV,125 FAQ
1.How can I place an order for 74AHC1G126GV,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHC1G126GV,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHC1G126GV,125 reliable?
The price and inventory of 74AHC1G126GV,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHC1G126GV,125 is usually 5 days.
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Once your 74AHC1G126GV,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHC1G126GV,125?
For technical support, including 74AHC1G126GV,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHC1G126GV,125 requirements.
6.How does Aetrix verify that 74AHC1G126GV,125 is sourced from the original manufacturer or authorized distributors?
All 74AHC1G126GV,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHC1G126GV,125 meets industry standards.
7.What is the process for return or replacement of 74AHC1G126GV,125?
All 74AHC1G126GV,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHC1G126GV,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHC1G126GV,125 part is unused and in its original packaging.
Return procedure for 74AHC1G126GV,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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