Nexperia USA Inc. 74AHCT126BQ,115
- Part No.:
- 74AHCT126BQ,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-VFQFN Exposed Pad
- Datasheet:
-
74AHCT126BQ,115.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14DHVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AHCT126BQ,115 from Nexperia is a quad 3-state buffer/line driver with TTL-compatible inputs, operating from 4.5 V to 5.5 V over -40 °C to +125 °C. It features 14-terminal DHVQFN package, 3.3 ns typical propagation delay (VCC = 5 V, CL = 15 pF), input overvoltage tolerance up to 5.5 V, and Schmitt-trigger inputs for noise immunity - used in industrial bus interface and level translation between 3.3 V and 5 V logic domains.
For engineers reviewing the 74AHCT126BQ,115 datasheet, 74AHCT126BQ,115 pinout, 74AHCT126BQ,115 application, or 74AHCT126BQ,115 equivalent, key selection criteria include TTL-level input compatibility, 3-state output timing (enable/disable times ≤ 9.0 ns), thermal-enhanced DHVQFN14 package for high-density PCBs, and guaranteed operation at 125 °C ambient.
Technical Context
This device implements four independent non-inverting buffers, each with active-HIGH output enable (nOE) controlling high-impedance tri-state output. Input voltage thresholds are fixed at VIH = 2.0 V and VIL = 0.8 V (TTL-compatible), enabling direct interfacing with legacy 5 V microcontrollers and FPGAs without level shifters.
Each channel supports bidirectional signal routing via 3-state control, with balanced tPLH/tPHL propagation delays and fast enable/disable transitions (ten ≤ 9.0 ns, tdis ≤ 11.5 ns at VCC = 5 V). The DHVQFN14 package includes an exposed thermal pad (non-electrical, optional GND connection) for improved thermal performance in compact industrial modules.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5 V logic rails and tolerates ±5% regulation drift. |
| Propagation Delay | 3.0 ns (typ) at VCC = 5 V, CL = 15 pF - enables reliable operation in 100+ MHz digital interfaces with tight timing margins. |
| Input Thresholds | VIH = 2.0 V, VIL = 0.8 V - matches TTL logic families, eliminating need for external level-shifting circuitry. |
| Output Drive | ±8 mA at VOH/VOL - sufficient to drive 50 pF loads across 10 cm PCB traces without signal integrity degradation. |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive auxiliary modules and industrial motor control enclosures. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - withstands handling and board assembly without additional protection components. |
| Power Dissipation | 500 mW max (derated above 98 °C) - supported by DHVQFN thermal pad for sustained operation in sealed enclosures. |
Pinout & Package
DHVQFN14 (SOT762-1) package: 2.5 mm × 3.0 mm × 0.85 mm body, 14 terminals, no leads, exposed thermal pad (terminal 7 is GND; pad is non-electrical but may be floated or connected to GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-HIGH enable for buffer 1 - drives output 1Y to high-impedance when HIGH; requires pull-down for default OFF-state. |
| 2 | VCC | Main supply rail - decoupling capacitor (100 nF) must be placed within 3 mm of this pin for stable switching. |
| 3 | 1A | Data input for buffer 1 - accepts voltages up to 5.5 V regardless of VCC, enabling mixed-voltage domain interfacing. |
| 4 | 4OE | Active-HIGH enable for buffer 4 - independent control allows selective channel isolation in multi-drop bus systems. |
| 5 | 1Y | Inverting-buffered output for input 1A - outputs HIGH/LOW matching 1A when 1OE = LOW; high-Z when 1OE = HIGH. |
| 6 | 4A | Data input for buffer 4 - identical electrical characteristics to 1A; supports daisy-chained signal distribution. |
| 7 | GND | Reference ground - connects to PCB ground plane; thermal pad (underside) improves heat dissipation but is not electrically tied. |
| 8 | 3Y | Output for buffer 3 - shares same timing specs as 1Y; critical for synchronized enable/disable in parallel data paths. |
| 9 | 3A | Data input for buffer 3 - Schmitt-trigger input provides 0.4 V hysteresis, rejecting sub-10 ns noise spikes on long traces. |
| 10 | 3OE | Active-HIGH enable for buffer 3 - enables per-channel power gating in low-power standby modes. |
| 11 | 4Y | Output for buffer 4 - matched propagation delay ensures skew < 0.5 ns across all four channels at 5 V. |
| 12 | 4A | Data input for buffer 4 - duplicate of pin 6; pin numbering confirms dual 4A assignment in functional diagram. |
| 13 | 4OE | Redundant enable pin for buffer 4 - matches pin 4; both serve same function per datasheet pin description table. |
| 14 | VCC | Second supply connection - reduces IR drop in high-current switching; must be independently decoupled. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible inputs | VIH = 2.0 V, VIL = 0.8 V - directly interfaces with 74LS, 74F, and legacy MCU GPIOs without external resistors or translators. |
| Schmitt-trigger inputs | 0.4 V hysteresis - suppresses contact bounce in switch interfaces and rejects EMI on unshielded cables in factory automation. |
| Overvoltage-tolerant inputs | Accepts up to 5.5 V regardless of VCC - allows safe connection to 5 V buses while powered from 3.3 V supplies in hybrid systems. |
| Thermal-enhanced DHVQFN | RθJA = 104 K/W (typ) - enables 2× higher continuous current vs. SO14 in space-constrained PLC I/O modules. |
| High-temp operation | Guaranteed functionality at +125 °C ambient - supports deployment in engine-control adjacent subsystems without derating. |
Applications
| Industrial Bus Interface | Legacy System Integration |
|---|---|
Use Scenario: Isolating and driving RS-485 transceiver enable lines in programmable logic controller (PLC) backplanes. IC Role / Device Role / Timing Role: Quad buffer provides independent 3-state control of four differential driver enables, synchronizing bus access across multiple slave nodes. Use Value: 9.0 ns enable time ensures deterministic arbitration window under 10 Mbps bus rates; thermal QFN package sustains 85 °C chassis temperature. |
Use Scenario: Interfacing 5 V TTL-encoded encoder signals to a 3.3 V FPGA-based motion controller. IC Role / Device Role / Timing Role: Level-translating buffer accepts 5 V inputs while powered from 3.3 V rail, preserving signal edge integrity without external biasing. Use Value: Input overvoltage tolerance eliminates need for series resistors or clamps; Schmitt action rejects 200 mV noise on 2 m motor cable runs. |
| Test Equipment Signal Routing | Automotive Diagnostic Interface |
Use Scenario: Multiplexing DUT test signals in automated boundary-scan test fixtures with shared probe cabling. IC Role / Device Role / Timing Role: Four independent 3-state buffers route stimulus/response paths under microcontroller control, preventing bus contention. Use Value: Matched propagation delays (< 0.5 ns skew) ensure simultaneous signal assertion across 4-channel JTAG/SWD debug ports. |
Use Scenario: Driving CAN transceiver standby pins and LIN bus pull-ups in vehicle telematics gateway ECUs. IC Role / Device Role / Timing Role: Buffer isolates low-power microcontroller GPIOs from higher-current bus conditioning circuits during sleep/wake transitions. Use Value: 125 °C rating supports placement near power converters; 2000 V HBM ESD protects against workshop ESD events during service. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT126PW,118 | TSSOP14 package (4.4 mm width); 7.3 mW/K thermal derating above 81 °C; identical electrical specs. | Better suited for manual rework and prototyping due to gull-wing leads; lower thermal performance than DHVQFN at >85 °C. | Select when board assembly uses standard reflow profiles and thermal management is handled externally. |
| SN74AHCT126PWR | Texas Instruments part; VCC range 4.5–5.5 V; tpd = 3.5 ns (typ); same pinout but different thermal pad design. | Qualified to AEC-Q100 Grade 2 (-40 °C to +105 °C); lacks 125 °C rating and DHVQFN thermal efficiency. | Choose only if TI supply chain alignment is required and full 125 °C operation is not needed. |
Compared with 74AHCT126PW,118 and SN74AHCT126PWR, the 74AHCT126BQ,115 delivers superior thermal performance in high-density layouts and guarantees operation at 125 °C - making it optimal for sealed industrial enclosures and under-hood auxiliary modules where airflow is restricted.
Availability
74AHCT126BQ,115 is available at Aetrix Electronics and suitable for industrial bus interface, legacy system integration, test equipment signal routing, and automotive diagnostic interface requiring stable component supply across extended temperature ranges.
Supply support for 74AHCT126BQ,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components with emphasis on reliability and energy efficiency.
The 74AHCT126BQ,115 belongs to Nexperia's advanced logic family designed for robust signal integrity in industrial automation, automotive subsystems, and test instrumentation where mixed-voltage interoperability and thermal resilience are critical.
FAQ
What is the maximum clock frequency supported by the 74AHCT126BQ,115?
The 74AHCT126BQ,115 is not a clocked device but a combinational buffer. Its usable signal frequency depends on propagation delay and load capacitance. With 3.0 ns typical tpd (VCC = 5 V, CL = 15 pF), it supports clean edge transmission up to ~160 MHz for single-bit paths, assuming proper termination and layout. System-level bandwidth is governed by board trace impedance and capacitive loading, not internal clocking.
Can the thermal pad on the DHVQFN package be left unconnected?
Yes - the exposed thermal pad (terminal 7 area) has no electrical function per datasheet note. It may remain floating, be soldered to a non-connected copper pour, or connected to GND. If connected to GND, ensure the land pattern remains isolated from other signals to avoid shorting; no electrical benefit is gained unless thermally coupled to a large ground plane for heat spreading.
Is the 74AHCT126BQ,115 pin-compatible with the 74AHC126BQ variant?
Yes - both share identical pinout, package (SOT762-1), and functional diagram. The key difference is input threshold: 74AHCT126BQ accepts TTL levels (VIH = 2.0 V), while 74AHC126BQ requires CMOS levels (VIH = 3.85 V at VCC = 5.5 V). Swapping them risks logic misreads if driven by 5 V TTL sources.
Does the 74AHCT126BQ,115 support hot-swap insertion?
No - the device lacks hot-swap protection circuitry such as slew-rate limiting or undervoltage lockout. Applying VCC before GND or inserting into a live backplane may cause latch-up or transient overstress. Always power-rail sequence GND → VCC, and use external hot-swap controllers if live insertion is required.
74AHCT126BQ,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHCT
- Package/Case:
- 14-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-DHVQFN (2.5x3)
74AHCT126BQ,115 FAQ
1.How can I place an order for 74AHCT126BQ,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHCT126BQ,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHCT126BQ,115 reliable?
The price and inventory of 74AHCT126BQ,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHCT126BQ,115 is usually 5 days.
3.What payment methods are accepted for 74AHCT126BQ,115?
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4.How is shipping managed for 74AHCT126BQ,115?
74AHCT126BQ,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AHCT126BQ,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHCT126BQ,115?
For technical support, including 74AHCT126BQ,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHCT126BQ,115 requirements.
6.How does Aetrix verify that 74AHCT126BQ,115 is sourced from the original manufacturer or authorized distributors?
All 74AHCT126BQ,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHCT126BQ,115 meets industry standards.
7.What is the process for return or replacement of 74AHCT126BQ,115?
All 74AHCT126BQ,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHCT126BQ,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHCT126BQ,115 part is unused and in its original packaging.
Return procedure for 74AHCT126BQ,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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