Nexperia USA Inc. 74AHCT126PW,118
- Part No.:
- 74AHCT126PW,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74AHCT126PW,118.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,132
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AHCT126PW,118 from Nexperia is a quad 3-state buffer/line driver with TTL-compatible inputs and CMOS outputs, operating from 4.5 V to 5.5 V supply, featuring 3.0 ns typical propagation delay at 5 V/15 pF, ±8 mA output drive, and overvoltage-tolerant inputs enabling mixed-voltage interfacing in industrial control backplanes.
For engineers reviewing the 74AHCT126PW,118 datasheet, 74AHCT126PW,118 pinout, 74AHCT126PW,118 application, or 74AHCT126PW,118 equivalent, this device serves as a level-translating bus driver in legacy TTL-to-CMOS interface circuits, high-speed data routing nodes, and bidirectional I/O expansion blocks where low static current (<2 μA) and precise enable timing (ten = 3.3 ns typ.) are critical.
Technical Context
This device implements four independent non-inverting buffers, each with active-HIGH 3-state output enable (nOE), allowing simultaneous bus isolation or parallel data forwarding. Input Schmitt-trigger action ensures noise immunity on slow-rising signals, while overvoltage tolerance up to 5.5 V enables safe interfacing with 3.3 V logic driving 5 V buses.
Its TTL-level input thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V at VCC = 4.5–5.5 V) guarantee compatibility with legacy 5 V TTL families, and its CMOS output structure delivers rail-to-rail swing with symmetrical rise/fall times under 5 ns at 15 pF load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - Ensures robust operation across industrial 5 V rails with ±5% tolerance. |
| Propagation Delay | 3.0 ns (typ.) at VCC = 5 V, CL = 15 pF - Enables reliable 160+ MHz data throughput in synchronous bus applications. |
| Output Drive | ±8 mA - Sustains signal integrity across 50 Ω transmission lines or multi-load fanout without external termination. |
| Input Thresholds | VIH ≥ 2.0 V, VIL ≤ 0.8 V - Guarantees clean recognition of standard TTL logic levels at full speed. |
| Static Current | 2.0 μA (max) at VCC = 5.5 V - Minimizes quiescent power in always-on control subsystems. |
| Operating Temp | −40 °C to +125 °C - Validated for under-hood automotive modules and industrial PLC I/O cards. |
| ESD Rating | HBM > 2000 V, CDM > 1000 V - Supports handling in uncontrolled assembly environments without special precautions. |
Pinout & Package
TSSOP14 plastic thin shrink small outline package (SOT402-1); 14-lead, 4.4 mm body width, 0.65 mm pitch; thermally enhanced for continuous 125 °C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (1–4) | Active-HIGH output enable per channel - Asserting HIGH disables corresponding output to high-Z, enabling shared bus arbitration. |
| 2, 5, 9, 12 | nA (1–4) | Data input per channel - TTL-compatible threshold allows direct connection to 74LS/74F outputs without level-shifting. |
| 3, 6, 8, 11 | nY (1–4) | CMOS output per channel - Delivers full-rail swing (0 V to VCC) with <5 ns transition time into 15 pF. |
| 7 | GND | Signal reference and return path - Must be low-inductance connected to system ground plane to maintain noise margin. |
| 14 | VCC | Positive supply - Requires local 100 nF ceramic decoupling within 5 mm to suppress switching transients. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-tolerant inputs | Accepts up to 5.5 V regardless of VCC - Enables safe 3.3 V microcontroller I/O driving 5 V bus segments. |
| Schmitt-trigger inputs | Hysteresis ≥ 0.3 V - Rejects >100 mV of noise on slow-switching control lines (e.g., reset, enable). |
| Low dynamic power | CPD = 12 pF - Limits switching power to <1.5 mW per channel at 10 MHz, easing thermal design. |
| Wide temperature range | −40 °C to +125 °C - Qualified for use in motor drives, power supplies, and outdoor telecom equipment. |
| Multiple package options | TSSOP14 (PW), SO14 (D), DHVQFN14 (BQ) - Supports layout flexibility from cost-sensitive through-hole to space-constrained SMT designs. |
Applications
| Industrial Bus Interface | Legacy System Upgrades |
|---|---|
|
Use Scenario: Isolating and buffering address/data lines between a modern ARM-based controller and legacy 5 V ISA-bus peripherals. IC Role / Device Role / Timing Role: Quad buffer provides direction-controlled, low-skew signal translation with precise 3-state timing (tdis = 6.9 ns typ.) to prevent bus contention during handshaking. Use Value: Eliminates need for discrete level shifters and reduces PCB layer count by consolidating four channels in one TSSOP14 footprint. |
Use Scenario: Replacing obsolete 74LS126 in aging test equipment requiring extended temperature support and lower power. IC Role / Device Role / Timing Role: Drop-in compatible buffer with identical pinout and TTL input behavior, but improved 125 °C rating and 10× lower ICC. Use Value: Extends field life of legacy instruments without redesign; supports recalibration cycles in hot enclosures. |
| Programmable Logic I/O Expansion | High-Speed Data Multiplexing |
|
Use Scenario: Expanding FPGA GPIO count to drive multiple 5 V sensors and actuators via shared parallel bus. IC Role / Device Role / Timing Role: 3-state outputs allow time-multiplexed access to eight devices using two 74AHCT126PW units under FPGA control. Use Value: Achieves deterministic 3.3 ns enable-to-output timing, enabling sub-100 ns bus arbitration windows. |
Use Scenario: Routing high-speed serial data (e.g., UART, SPI clock) between dual microcontrollers sharing a common debug header. IC Role / Device Role / Timing Role: Non-inverting buffer with matched tPLH/tPHL ensures <0.2 ns skew between channels for phase-critical clock distribution. Use Value: Maintains signal integrity at 25 MHz without added jitter, avoiding timing violations in synchronized systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT126D,118 | SO14 package (3.9 mm width); 10.1 mW/K thermal derating above 100 °C vs. 7.3 mW/K for PW | Better suited for wave-soldered industrial boards; less suitable for fine-pitch automated assembly | Select when mechanical robustness and hand-solderability outweigh board space constraints. |
| SN74AHCT126PWR | Texas Instruments part; identical logic function and DC specs, but tpd = 3.5 ns (min) vs. 3.0 ns (typ.) and higher ICC (5 μA max) | Valid for TI-centric BOMs; requires validation of enable timing margins in high-frequency bus arbitration | Select only if TI supply chain alignment or existing qualification overrides Nexperia's lower propagation delay and leakage. |
Compared with 74AHCT126D,118, the PW variant offers superior thermal performance in compact layouts; compared with SN74AHCT126PWR, it delivers tighter propagation delay consistency and lower static current-critical for battery-backed or thermally constrained systems.
Availability
74AHCT126PW,118 is available at Aetrix Electronics and suitable for industrial automation interfaces, legacy system upgrades, and programmable logic I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AHCT126PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AHCT series targets robust, pin-compatible replacements for legacy TTL logic in mixed-voltage systems, emphasizing interoperability, wide temperature operation, and low-power CMOS efficiency.
FAQ
Is 74AHCT126PW,118 compatible with 3.3 V microcontroller GPIOs?
Yes - its inputs tolerate up to 5.5 V regardless of VCC, so 3.3 V MCU outputs can directly drive nA pins without level shifters. However, outputs swing from 0 V to VCC; if VCC = 5 V, external voltage dividers or clamping diodes are required before connecting to 3.3 V-only inputs.
What is the maximum capacitive load this device can drive reliably?
It is characterized up to 50 pF (tpd = 4.3 ns max at VCC = 5 V), but sustained loads >30 pF increase transition time and may cause ringing. For >50 pF, add series source termination (22–33 Ω) near the driver output to dampen reflections and maintain signal integrity.
Can all four buffers be enabled simultaneously without thermal issues?
Yes - at 5 V and 25 °C, total ICC remains <10 μA (quiescent). Even with all outputs sourcing/sinking 8 mA, power dissipation stays below 100 mW in TSSOP14, well within the 500 mW Ptot limit at 125 °C ambient, provided PCB copper area meets Nexperia's recommended thermal pad layout.
Does this part support hot-swap or live-insertion?
No - it lacks powered-off protection or Ioff circuitry. Applying input signals while VCC is unpowered may forward-bias internal ESD diodes, causing latch-up or damage. Always sequence VCC before asserting any inputs in hot-swap systems.
74AHCT126PW,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AHCT
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
74AHCT126PW,118 FAQ
1.How can I place an order for 74AHCT126PW,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHCT126PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHCT126PW,118 reliable?
The price and inventory of 74AHCT126PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHCT126PW,118 is usually 5 days.
3.What payment methods are accepted for 74AHCT126PW,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AHCT126PW,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AHCT126PW,118?
74AHCT126PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AHCT126PW,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHCT126PW,118?
For technical support, including 74AHCT126PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHCT126PW,118 requirements.
6.How does Aetrix verify that 74AHCT126PW,118 is sourced from the original manufacturer or authorized distributors?
All 74AHCT126PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHCT126PW,118 meets industry standards.
7.What is the process for return or replacement of 74AHCT126PW,118?
All 74AHCT126PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHCT126PW,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHCT126PW,118 part is unused and in its original packaging.
Return procedure for 74AHCT126PW,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AHCT126PW,118 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

