NXP Semiconductors 74AHCT2G126GD,125
- Part No.:
- 74AHCT2G126GD,125
- Manufacturer:
- NXP Semiconductors
- Package:
- 8-XFDFN
- Datasheet:
-
74AHCT2G126GD,125.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 8XSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AHCT2G126GD,125 from Nexperia is a dual 3-state buffer/line driver with TTL-compatible inputs and overvoltage-tolerant inputs up to 5.5 V, operating across 4.5–5.5 V supply range, delivering 8 ns typical propagation delay at 5 V/50 pF, and rated for -40 °C to +125 °C industrial temperature range - used in bidirectional bus interfacing and voltage-level translation between mixed-supply subsystems.
For engineers reviewing the 74AHCT2G126GD,125 datasheet, 74AHCT2G126GD,125 pinout, 74AHCT2G126GD,125 application, or 74AHCT2G126GD,125 equivalent, key selection considerations include TTL input threshold compatibility (VIH = 2.0 V min), 3-state enable timing (ten = 5.1–9.5 ns), output drive strength (±8 mA at VOH/VOL), and XSON8 package thermal performance (Ptot = 250 mW).
Technical Context
This device implements two independent non-inverting buffers, each with active-HIGH 3-state output enable (1OE, 2OE), enabling bidirectional bus control without external logic. Input thresholds conform to TTL levels (VIH ≥ 2.0 V, VIL ≤ 0.8 V at VCC = 4.5–5.5 V), ensuring direct compatibility with legacy 5 V logic families.
Each buffer supports rail-to-rail output swing (VOH ≥ 3.94 V, VOL ≤ 0.36 V at IO = ±8 mA, VCC = 4.5 V), maintains symmetrical output impedance, and features overvoltage-tolerant inputs (up to 5.5 V regardless of VCC), allowing safe operation in mixed-voltage domains such as 3.3 V controller driving 5 V peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5–5.5 V - ensures compatibility with standard 5 V logic rails and tolerates nominal 5 V ±10% variation. |
| Input Threshold (VIH/VIL) | VIH ≥ 2.0 V, VIL ≤ 0.8 V - guarantees reliable recognition of TTL-level signals without level-shifting circuitry. |
| Propagation Delay (tpd) | 3.4–7.5 ns (CL = 15–50 pF, VCC = 4.5–5.5 V) - enables high-speed data routing in sub-100 MHz digital interfaces. |
| Output Drive (IO) | ±8 mA - sufficient to drive standard 50 pF loads and multiple CMOS/TTL inputs while maintaining signal integrity. |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules, industrial PLC I/O, and extended-range embedded controllers. |
| Power Dissipation (Ptot) | 250 mW - supports continuous operation in compact XSON8 package with defined derating above 99 °C. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - meets IEC 61000-4-2 Level 2 requirements for board-level robustness. |
Pinout & Package
XSON8 (SOT996-2) plastic ultra-thin small outline no-lead package: 1.35 mm × 1.35 mm body, 0.5 mm pitch, 0.45 mm max height, wettable flank terminals for automated optical inspection (AOI) and improved solder-joint reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-HIGH output enable for Buffer 1 - drives 1Y to high-impedance when LOW, enables pass-through when HIGH. |
| 2 | 1A | Data input for Buffer 1 - accepts TTL/CMOS-compatible signals; overvoltage tolerant to 5.5 V. |
| 3 | GND | Ground reference (0 V) - shared return path for both buffers and supply decoupling. |
| 4 | 2A | Data input for Buffer 2 - electrically isolated from 1A; identical input characteristics. |
| 5 | 2OE | Active-HIGH output enable for Buffer 2 - independently controls 2Y high-impedance state. |
| 6 | 2Y | Inverting output for Buffer 2 - not applicable; this is non-inverting buffer; 2Y follows 2A when 2OE = HIGH. |
| 7 | 1Y | Non-inverting output for Buffer 1 - mirrors 1A when 1OE = HIGH; high-Z when 1OE = LOW. |
| 8 | VCC | Positive supply rail - powers both buffers; must be decoupled locally with ≤100 nF ceramic capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible input thresholds | VIH ≥ 2.0 V, VIL ≤ 0.8 V at 4.5–5.5 V - eliminates need for external level shifters when interfacing with legacy 5 V microcontrollers. |
| Overvoltage-tolerant inputs | Withstand up to 5.5 V regardless of VCC - enables safe connection to higher-voltage buses without clamping diodes or resistors. |
| Symmetrical output impedance | Matched rise/fall times (tPLH ≈ tPHL) - reduces signal distortion and jitter in high-speed data lines. |
| Industrial temperature range | -40 °C to +125 °C operation - supports deployment in engine control units, motor drives, and outdoor industrial gateways. |
| Low dynamic power dissipation | CPD = 10 pF per buffer - limits switching current and heat generation in battery-powered or thermally constrained designs. |
Applications
| Industrial Sensor Interface | Legacy Microcontroller Bus Extension |
|---|---|
|
Use Scenario: Isolating and buffering analog-to-digital converter (ADC) status lines and configuration registers in a 5 V sensor node with 3.3 V host MCU. IC Role / Device Role / Timing Role: Dual 3-state buffer provides direction-controlled signal routing between mismatched voltage domains while preventing bus contention during configuration writes. Use Value: Overvoltage-tolerant inputs accept 5 V ADC outputs directly; TTL thresholds ensure reliable enable/disable signaling from 3.3 V GPIOs. |
Use Scenario: Expanding address/data bus capacity of an 8051-based control system by adding peripheral memory or I/O chips. IC Role / Device Role / Timing Role: Acts as bi-directional bus driver with independent enable control, synchronizing data flow between CPU and external devices using standard 5 V TTL timing. Use Value: 3.4 ns min propagation delay at 5 V enables stable operation up to 80 MHz bus clock rates with margin for trace delays. |
| Automotive Body Control Module | Programmable Logic Interconnect |
|
Use Scenario: Driving LED driver ICs and relay control signals from a 5 V CAN microcontroller in a BCM where ESD immunity and thermal stability are critical. IC Role / Device Role / Timing Role: Provides noise-immune signal conditioning and current gain for low-side switch control lines, with independent enable per channel. Use Value: HBM > 2000 V and -40 °C to +125 °C rating meet ISO 16750-2 environmental stress requirements for passenger compartment electronics. |
Use Scenario: Interfacing FPGA I/O banks (3.3 V LVCMOS) with external 5 V programmable logic devices or discrete glue logic in reconfigurable systems. IC Role / Device Role / Timing Role: Serves as voltage-translating buffer with precise timing control, enabling synchronous handshaking between heterogeneous logic families. Use Value: Matched enable/disable timing (ten/tdis ≤ 9.5 ns) ensures deterministic bus arbitration and avoids metastability in multi-clock domain crossings. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AHCT2G125DC,125 | Identical pinout and electrical specs, but uses VSSOP8 (SOT765-1) package - 2.3 mm body width, 0.5 mm pitch, taller profile (1.1 mm height). | Preferred where board space allows larger footprint but higher standoff or manual rework accessibility is needed. | Select for prototyping or low-volume production where VSSOP8 handling and thermal mass simplify assembly. |
| SN74LVC2G126DBVR | 3.3 V only supply (1.65–5.5 V), LVTTL inputs (VIH = 2.0 V @ VCC = 3.3 V), slightly faster tpd (2.5 ns typ @ 3.3 V/50 pF). | Better suited for modern 3.3 V systems; lacks full 5 V tolerance on inputs and outputs. | Choose when interfacing exclusively with 3.3 V logic and lower static power (< 1 μA ICC) is prioritized over 5 V bus compatibility. |
Compared with 74AHCT2G126GD,125, the VSSOP8 alternative offers easier handling and thermal margin but occupies ~2.5× more PCB area, while the LVC variant trades 5 V robustness for lower voltage operation and marginally better speed at 3.3 V - making the XSON8 version optimal for space-constrained, mixed-voltage industrial modules requiring proven 5 V interoperability.
Availability
74AHCT2G126GD,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, legacy microcontroller bus extensions, and programmable logic interconnects requiring stable component supply across extended temperature and mixed-voltage environments.
Supply support for 74AHCT2G126GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for automotive, industrial, and consumer applications.
The 74AHCT series belongs to Nexperia's advanced logic portfolio, engineered specifically for robust, low-power, mixed-voltage interfacing in harsh-environment embedded systems - emphasizing TTL compatibility, wide temperature operation, and high ESD resilience.
FAQ
Is 74AHCT2G126GD,125 pin-compatible with 74AHCT2G126DC,125?
No - 74AHCT2G126GD,125 uses XSON8 (SOT996-2) with 0.5 mm pitch and bottom-exposed thermal pad, while 74AHCT2G126DC,125 uses VSSOP8 (SOT765-1) with gull-wing leads and 0.5 mm pitch but different land pattern and soldering profile. Footprints and reflow profiles are not interchangeable.
Can 74AHCT2G126GD,125 operate reliably at 3.3 V supply?
No - the 74AHCT variant is specified only for 4.5–5.5 V operation. At 3.3 V, VIH minimum (2.0 V) is met, but VOH drops below TTL-compliant levels and propagation delay increases significantly beyond datasheet limits; use 74AHC2G126GD,125 or 74LVC2G126 for 3.3 V systems.
What is the maximum capacitive load this device can drive while maintaining timing specs?
The device is characterized up to 50 pF (Table 8), with tpd = 4.8–7.5 ns and ten/tdis = 5.1–9.5 ns at VCC = 4.5–5.5 V. Driving >50 pF violates guaranteed timing; for heavier loads, add series termination or reduce edge rate via input RC filtering to avoid overshoot and timing violations.
Does the XSON8 package require special PCB layout considerations?
Yes - the XSON8 (SOT996-2) has a center thermal pad that must be soldered to a dedicated copper pour with ≥4 thermal vias (0.3 mm diameter) to GND for thermal management and mechanical reliability. Pad dimensions must match the 0.9 × 0.9 mm exposed pad; insufficient solder paste volume causes tombstoning or voiding.
74AHCT2G126GD,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AHCT
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (2x3)
74AHCT2G126GD,125 FAQ
1.How can I place an order for 74AHCT2G126GD,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AHCT2G126GD,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AHCT2G126GD,125 reliable?
The price and inventory of 74AHCT2G126GD,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AHCT2G126GD,125 is usually 5 days.
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Once your 74AHCT2G126GD,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AHCT2G126GD,125?
For technical support, including 74AHCT2G126GD,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AHCT2G126GD,125 requirements.
6.How does Aetrix verify that 74AHCT2G126GD,125 is sourced from the original manufacturer or authorized distributors?
All 74AHCT2G126GD,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AHCT2G126GD,125 meets industry standards.
7.What is the process for return or replacement of 74AHCT2G126GD,125?
All 74AHCT2G126GD,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AHCT2G126GD,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AHCT2G126GD,125 part is unused and in its original packaging.
Return procedure for 74AHCT2G126GD,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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