Nexperia USA Inc. 74AUP1G00GF,132

Overview

74AUP1G00GF,132 from Nexperia is a single 2-input NAND gate logic IC operating from 0.8 V to 3.6 V supply, with typical propagation delay of 2.9 ns at 3.3 V and output drive capability of ±4 mA, used in low-power portable interface and signal conditioning circuits.

For engineers reviewing the 74AUP1G00GF,132 datasheet, 74AUP1G00GF,132 pinout, 74AUP1G00GF,132 application, or 74AUP1G00GF,132 equivalent, key selection criteria include ultra-low static current (0.9 µA max), rail-to-rail input compatibility, AUP logic family timing behavior, and DFN1010-6 package thermal performance.

Technical Context

This device implements standard positive-logic NAND functionality using silicon-gate CMOS process technology. It supports dynamic operation down to 0 Hz (DC-coupled) and features Schmitt-trigger inputs only in specific variants - this part uses standard CMOS inputs without hysteresis.

The AUP family targets battery-powered systems requiring sub-1 µA I_CC at 3.3 V and full 0.8–3.6 V V_CC range compliance. Input thresholds are referenced to V_CC, enabling interoperability across mixed-voltage domains without level shifters.

Key Specifications

Pinout & Package

Supplied in a 6-pin DFN1010-6 (1.0 mm × 1.0 mm, 0.4 mm pitch) package with exposed thermal pad, optimized for space-constrained PCB layouts and thermal dissipation in high-density modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with SN74LVC1G00DBVR, 74AUP1G00GF,132 trades drive strength for 90% lower static power and smaller size; versus 74LVC1G00GW,125, it adds thermal pad and NC pin for improved manufacturability and noise immunity in dense layouts.

Availability

74AUP1G00GF,132 is available at Aetrix Electronics and suitable for smart wearable sensor hubs, industrial PLC I/O expanders, and automotive body control modules requiring stable component supply and long-term lifecycle support.

Supply support for 74AUP1G00GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The AUP (Advanced Ultra-low Power) logic family was designed specifically for energy-constrained edge devices requiring guaranteed timing and rail-to-rail interoperability across mixed-voltage systems.

FAQ

Is 74AUP1G00GF,132 compatible with 1.2 V supply rails?

Yes. The device is fully specified from 0.8 V to 3.6 V, including guaranteed operation at 1.2 V. At this voltage, propagation delay increases to 10.2 ns (max), and output drive reduces to ±1.5 mA, but all logic thresholds and DC parameters remain valid per datasheet Section 7.1.

Does the NC pin require grounding or can it be left floating?

The NC (pin 6) is internally unconnected. Nexperia recommends leaving it floating per datasheet guidance; however, tying it to GND improves ESD robustness and reduces crosstalk in high-frequency layouts, with no functional impact.

Can 74AUP1G00GF,132 drive a 50 Ω transmission line directly?

It can drive a 50 Ω load short-term (e.g., test point stub), but sustained 50 Ω termination exceeds its ±4 mA rating at 3.3 V. For reliable 50 Ω line driving, use a dedicated buffer or series-terminate with 33 Ω resistor to limit current while preserving signal integrity.

What is the maximum recommended PCB trace length for 74AUP1G00GF,132 outputs?

For signal integrity below 100 MHz, traces up to 50 mm (with 50 Ω characteristic impedance and proper return path) maintain <10% overshoot. Beyond that, add series termination or reduce fanout; the 2.9 ns t_PD implies usable bandwidth up to ~170 MHz before interconnect dominates timing.