NXP Semiconductors 74AUP1G00GM,115

Overview

74AUP1G00GM,115 from Nexperia is a single 2-input NAND gate in XSON6 (SOT886) package, operating from 0.8 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C. It delivers ultra-low static ICC ≤ 1.4 μA (max) and propagation delay as low as 1.0 ns at 3.6 V/5 pF, enabling use in battery-powered sensor interface and level-shifting logic in space-constrained IoT edge nodes.

For engineers reviewing the 74AUP1G00GM,115 datasheet, 74AUP1G00GM,115 pinout, 74AUP1G00GM,115 application, or 74AUP1G00GM,115 equivalent, key selection criteria include its 6-terminal no-lead XSON6 footprint, IOFF-enabled hot-swap capability, Schmitt-trigger input hysteresis, and sub-2 ns propagation delay across 0.8–3.6 V - critical for low-voltage mixed-signal timing integrity and power-gated subsystem control.

Technical Context

This device implements a single CMOS NAND function with Schmitt-trigger inputs, providing hysteresis (ΔV ≈ 0.1–0.3 V depending on VCC) to reject slow-rising or noisy signals. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA (max) and enabling safe partial power-down in multi-rail systems.

It supports JEDEC-compliant voltage ranges (JESD8-12 through JESD8C), operates over full industrial and extended automotive temperature grades (–40 °C to +125 °C), and maintains stable VIH/VIL thresholds across VCC (e.g., VIH ≥ 2.0 V at 3.0–3.6 V; VIL ≤ 0.9 V), ensuring interoperability with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad optional; side-wettable flanks not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with SN74LVC1G00DBVR and 74LVC1G00GW,125, the 74AUP1G00GM,115 uniquely combines sub-1.5 μA static current, Schmitt-trigger noise rejection, and IOFF-enabled hot-swap safety - making it the only option qualified for always-on, multi-rail, and ultra-low-power edge sensing.

Availability

74AUP1G00GM,115 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control modules, and low-power wearable electronics requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP1G00GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and discrete components, with leadership in advanced packaging and automotive-grade qualification.

The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-voltage, ultra-low-power logic applications in battery-operated and energy-sensitive systems - prioritizing sub-microamp ICC, wide VCC scalability, and robust IOFF behavior.

FAQ

Does the 74AUP1G00GM,115 support true 0.8 V logic operation?

Yes. The device is fully specified down to 0.8 V supply, with VIH ≥ 0.70×VCC and VIL ≤ 0.30×VCC at that voltage, and propagation delay ≤17.5 ns (typ) at CL = 5 pF. All static and dynamic parameters in Table 7 and Table 8 are validated at 0.8 V, confirming functional correctness and timing compliance in sub-1 V systems.

Can the n.c. pin on the SOT886 package be grounded or left floating?

The n.c. (no-connect) pin is internally unconnected and must remain electrically floating - neither grounded nor tied to VCC. Routing or soldering to this terminal may cause mechanical stress or unintended coupling; Nexperia's package drawings and reliability testing assume it is left unconnected and unpopulated on the PCB.

How does IOFF behave when VCC ramps from 0 V to nominal voltage?

IOFF activates when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.4 V. During this transition, output leakage is limited to ±0.75 μA max (ΔIOFF), preventing backflow into powered downstream circuits. This behavior is verified per JESD78 Class II latch-up testing and documented in Table 7 under "IOFF power-off leakage current".

Is the Schmitt-trigger hysteresis voltage fixed or VCC-dependent?

Hysteresis is VCC-dependent: typical ΔV = 0.15 V at VCC = 1.2 V, increasing to ~0.3 V at VCC = 3.3 V. This scaling ensures consistent noise margin percentage (≈12–15 % of VCC) across the full 0.8–3.6 V range, as confirmed by VIH/VIL min/max values in Table 7 across all VCC bins and temperature grades.