Nexperia USA Inc. 74AUP1G00GM,132

Overview

74AUP1G00GM,132 from Nexperia is a single 2-input NAND gate in XSON6 (SOT886) package with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V supply, delivering propagation delay as low as 1.0 ns at 3.6 V (CL = 5 pF), and supporting -40 °C to +125 °C ambient range for industrial sensor interface and low-power logic level translation.

For engineers reviewing the 74AUP1G00GM,132 datasheet, 74AUP1G00GM,132 pinout, 74AUP1G00GM,132 application, or 74AUP1G00GM,132 equivalent, key selection criteria include IOFF-enabled partial power-down capability, sub-1 μA max ICC across full VCC range, Schmitt-trigger noise immunity on both inputs, and compatibility with 0.8 V logic systems in space-constrained portable electronics.

Technical Context

This device implements standard positive-logic NAND function (Y = NOT(A AND B)) with Schmitt-trigger input thresholds enabling robust operation under slow-rising or noisy signal conditions. Input hysteresis is inherent to the Schmitt action and varies with VCC - e.g., VIH − VIL ≈ 0.25×VCC at 0.8 V and ≥0.4 V at 3.6 V.

The IOFF circuit actively disables output when VCC = 0 V, limiting backflow current to ±0.75 μA maximum, and supports hot-insertion and multi-rail power sequencing. All inputs tolerate up to 3.6 V regardless of VCC, enabling level-shifting between disparate supply domains.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; wettable flanks not present; thermal pad absent; pin 1 index located on lower-left corner below marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with SN74LVC1G00DBVR and 74LVC1G00GW,125, the 74AUP1G00GM,132 uniquely delivers sub-1 μA ICC, Schmitt noise immunity, and guaranteed 0.8 V operation - making it the only choice for battery-critical, noise-prone, or multi-voltage rail designs where size and power are constrained.

Availability

74AUP1G00GM,132 is available at Aetrix Electronics and suitable for industrial sensor interface, low-power wearable control, and automotive body control requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G00GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line targets ultra-low-power digital logic applications in portable, battery-powered, and thermally constrained systems - emphasizing sub-1 μA static current, wide VCC scalability, and robust IO architecture.

FAQ

Does the 74AUP1G00GM,132 support true bidirectional level shifting?

No. It is a unidirectional logic gate: inputs accept 0–3.6 V regardless of VCC, but output swing is referenced to VCC and cannot exceed it. For true bidirectional translation (e.g., I²C), a dedicated level shifter like NXSA5180 must be used instead.

Can Pin 5 (n.c.) be grounded or tied to VCC for improved thermal performance?

No. Pin 5 is internally unconnected and must remain floating per datasheet. Connecting it risks parasitic conduction paths or latch-up. Thermal performance is defined solely by the package's 1.0 × 1.45 mm body and PCB copper area under the thermal pad (absent in SOT886).

What is the minimum load capacitance for guaranteed tpd specification?

The propagation delay is characterized down to CL = 5 pF. Below this, delay decreases further but is not guaranteed or tested. For designs with <5 pF net capacitance (e.g., short traces to high-impedance inputs), actual tpd may be ≤0.8 ns at 3.6 V, but timing margins should still use the 5 pF spec value.

Is the Schmitt-trigger hysteresis adjustable via external components?

No. Hysteresis is fixed by internal transistor sizing and process parameters; it scales with VCC (e.g., ~200 mV at 0.8 V, ~400 mV at 3.6 V) and cannot be modified externally. No pins, resistors, or bias networks alter the threshold behavior.