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Nexperia USA Inc. 74AUP1G00GS,132

Part No.:
74AUP1G00GS,132
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
6-XFDFN
Datasheet:
Aetrix74AUP1G00GS,132.pdf
Description:
IC GATE NAND 1CH 2-INP 6XSON
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:5,000

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Product details

Overview

74AUP1G00GS,132 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering propagation delay as low as 1.0 ns at 3.6 V (CL = 5 pF), ICC ≤ 1.4 μA max over –40 °C to +125 °C, and IOFF-enabled partial power-down protection for mixed-voltage system interfacing in portable sensor nodes and low-power MCU peripherals.

For engineers reviewing the 74AUP1G00GS,132 datasheet, 74AUP1G00GS,132 pinout, 74AUP1G00GS,132 application, or 74AUP1G00GS,132 equivalent, this device supports ultra-low-power logic level translation, noise-immune signal conditioning, and hot-swap-safe I/O isolation in space-constrained battery-powered designs requiring guaranteed VIH/VIL thresholds and sub-100 nW static power.

Technical Context

The 74AUP1G00GS,132 implements standard positive-logic NAND functionality with hysteresis on both inputs (Schmitt-trigger), enabling robust operation with slow-rising or noisy signals. Its IOFF circuit actively disables outputs when VCC = 0 V, preventing backflow current during partial power-down sequences.

It complies with JEDEC standards JESD8-12 through JESD8C across its full 0.8–3.6 V range and supports ESD immunity per HBM Class 3A (>5000 V) and CDM Class C3 (>1000 V), with input tolerance up to 3.6 V independent of VCC.

Key Specifications

Parameter Value and Actual Design Meaning
Logic Function Single 2-input NAND gate with true Schmitt-trigger inputs for noise margin & slow-edge tolerance
Supply Voltage Range 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains
Propagation Delay 1.0 ns min / 3.6 ns max at VCC = 3.6 V, CL = 5 pF - supports >200 MHz toggle rates in low-load conditions
ICC (max) 1.4 μA at –40 °C to +125 °C - ensures sub-microwatt static power in always-on monitoring circuits
IOFF Leakage ±0.75 μA max at VCC = 0 V - prevents destructive back-current during power sequencing in multi-rail systems
Operating Temperature –40 °C to +125 °C - qualified for under-hood automotive, industrial control, and extended-range IoT edge nodes
ESD Rating HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in handheld and wearable interfaces

Pinout & Package

XSON6 package (SOT1202): plastic extremely thin small outline, no leads, 6 terminals, body size 1.0 × 1.0 × 0.35 mm, side-wettable flanks not present (distinct from SOT8065-1).

Pin/Terminal Circuit Role Design Meaning
A Data input First Schmitt-triggered NAND input; accepts 0–3.6 V regardless of VCC
B Data input Second Schmitt-triggered NAND input; identical voltage tolerance and hysteresis to Pin A
GND Ground reference 0 V return path for all internal logic and output drivers; must be low-impedance
n.c. No connection Internally unconnected terminal; left floating or tied to GND per layout best practice
VCC Supply voltage Primary power rail (0.8–3.6 V); powers internal logic and enables IOFF control when de-asserted
Y Data output Active-low NAND output; drives CMOS loads up to ±4 mA at 3.0 V; IOFF disables output when VCC = 0 V

Key Features

Feature Design Value
Schmitt-trigger inputs Enables reliable switching with slow or noisy signals (e.g., mechanical switch debouncing, analog sensor thresholds)
IOFF partial power-down Prevents back-current flow when VCC is off, critical for hot-plug and multi-voltage domain isolation
Overvoltage-tolerant I/O Inputs accept up to 3.6 V even at VCC = 0.8 V - simplifies level-shifting in mixed-supply systems
Ultra-low ICC Max 1.4 μA over full temperature range - extends battery life in always-on wake-up logic and sensor hubs
JEDEC-compliant voltage ranges Validated across five JEDEC sub-ranges (JESD8-12 to JESD8C) - guarantees interoperability in legacy and new designs

Applications

Industrial Sensor Interface Portable Medical Device Logic

Use Scenario: Signal conditioning for analog sensor outputs feeding an ultra-low-power microcontroller ADC trigger.

IC Role / Device Role / Timing Role: NAND gate configured as inverter with Schmitt-trigger input cleans noisy thermistor or photodiode signals before wake-up interrupt assertion.

Use Value: Eliminates external RC filtering and reduces BOM count while maintaining <1.5 μA total quiescent current in sleep mode.

Use Scenario: Power sequencing control in a wearable ECG patch with separate battery management and signal processing rails.

IC Role / Device Role / Timing Role: Enables safe isolation of BLE radio enable line during main SoC power-down using IOFF behavior.

Use Value: Prevents reverse current injection into powered-down subsystems, avoiding latch-up and extending recharge cycle life.

Automotive Body Control Module IoT Edge Node Wake-Up Logic

Use Scenario: Debouncing door latch switch inputs in a 12 V vehicle platform with 3.3 V domain MCU.

IC Role / Device Role / Timing Role: Acts as noise-immune digital buffer between mechanical switch and CAN/LIN transceiver enable logic.

Use Value: Withstands automotive load dump transients up to 3.6 V on inputs while consuming <2 μA at 125 °C ambient.

Use Scenario: Low-power motion-triggered wake-up for LoRaWAN environmental sensor node.

IC Role / Device Role / Timing Role: Combines PIR sensor output and timer signal to generate precise wake pulse for MCU boot sequence.

Use Value: Delivers 1.0 ns propagation delay at 1.8 V supply, enabling sub-10 μs response time without compromising 10-year battery life.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC1G00DBVR Wider VCC range (1.65–5.5 V); no Schmitt-trigger inputs; higher ICC (10 μA typical) Lacks noise immunity for slow edges; unsuitable for direct mechanical switch interfacing Select only if interfacing with 5 V logic or where Schmitt action is unnecessary
74LVC1G00GW,125 TSSOP5 package (SOT353-1); same logic function but larger footprint (2.2 × 1.35 mm vs. 1.0 × 1.0 mm) Less suitable for space-constrained wearables or high-density PCBs Choose when hand-soldering or test probing is required; XSON6 is reflow-only

Compared with SN74LVC1G00DBVR and 74LVC1G00GW,125, the 74AUP1G00GS,132 uniquely combines Schmitt-trigger inputs, sub-2 μA ICC, and 1.0 mm² XSON6 packaging-making it optimal for miniaturized, noise-prone, battery-critical systems where timing predictability and power integrity are non-negotiable.

Availability

74AUP1G00GS,132 is available at Aetrix Electronics and suitable for industrial sensor interface, portable medical device logic, and automotive body control modules requiring stable component supply across extended temperature and ultra-low-power operation.

Supply support for 74AUP1G00GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for power, space, and reliability.

The 74AUP (Advanced Ultra-low Power) family targets battery-operated and energy-sensitive applications, emphasizing minimal static/dynamic power, wide voltage compatibility, and robustness in harsh environments.

FAQ

Does the 74AUP1G00GS,132 support true bidirectional level shifting?

No. It is a unidirectional logic gate: inputs accept 0–3.6 V regardless of VCC, but the output Y is referenced to VCC and cannot drive a higher-voltage rail. For bidirectional translation, a dedicated level shifter like NXSL0104 must be used.

Can Pin n.c. be used as a thermal pad or grounded for improved thermal performance?

No. Pin 5 (n.c.) is internally unconnected and not bonded. Grounding it provides no thermal benefit and may risk solder bridging or unintended coupling. Thermal dissipation relies solely on the exposed die pad under the package body per SOT1202 layout guidelines.

What is the minimum recommended trace width for the VCC and GND connections in high-reliability automotive layouts?

For automotive AEC-Q200 compliance, Nexperia recommends ≥0.25 mm (10 mil) trace width for VCC and GND on outer layers, with dedicated inner-layer planes preferred. The XSON6's low-inductance design minimizes sensitivity, but proper decoupling (100 nF X7R ceramic within 2 mm of pins 3 and 6) remains mandatory.

How does the Schmitt-trigger hysteresis vary across the 0.8–3.6 V supply range?

Hysteresis is proportional to VCC: typically 10–15 % of VCC. At 0.8 V, hysteresis ≈ 80–120 mV; at 3.6 V, ≈ 360–540 mV. This ensures consistent noise rejection across all supported voltages without requiring external hysteresis components.

74AUP1G00GS,132 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AUP
Package/Case:
6-XFDFN
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
NAND Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
-
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
4mA, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
6.5ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
6-XSON, SOT1202 (1x1)

74AUP1G00GS,132 FAQ

1.How can I place an order for 74AUP1G00GS,132 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP1G00GS,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP1G00GS,132 reliable?

The price and inventory of 74AUP1G00GS,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G00GS,132 is usually 5 days.

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74AUP1G00GS,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP1G00GS,132 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP1G00GS,132?

For technical support, including 74AUP1G00GS,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G00GS,132 requirements.

6.How does Aetrix verify that 74AUP1G00GS,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP1G00GS,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G00GS,132 meets industry standards.

7.What is the process for return or replacement of 74AUP1G00GS,132?

All 74AUP1G00GS,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G00GS,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP1G00GS,132 part is unused and in its original packaging.

Return procedure for 74AUP1G00GS,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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