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Nexperia USA Inc. 74AUP1G00GW,125
- Part No.:
- 74AUP1G00GW,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74AUP1G00GW,125.pdf
- Description:
- IC GATE NAND 1CH 2-INP 5TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:23,871
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Product details
Overview
74AUP1G00GW,125 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering propagation delay as low as 1.0 ns at 3.6 V (CL = 5 pF), ICC ≤ 0.9 μA max, and IOFF-enabled partial power-down capability for battery-powered IoT sensor nodes and portable logic interfacing.
For engineers reviewing the 74AUP1G00GW,125 datasheet, 74AUP1G00GW,125 pinout, 74AUP1G00GW,125 application, or 74AUP1G00GW,125 equivalent, this device supports ultra-low-voltage logic translation in space-constrained wearables, provides robust noise immunity in noisy industrial control I/O expansion, and enables safe hot-swap operation via IOFF in modular power management subsystems.
Technical Context
The 74AUP1G00GW,125 implements standard positive-logic NAND functionality (Y = NOT(A AND B)) with Schmitt-trigger input thresholds-VIH ≥ 0.65×VCC and VIL ≤ 0.35×VCC across 0.9–1.95 V supply range-ensuring reliable signal conditioning for slow-rising signals from mechanical switches or RC networks. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA.
Dynamic performance is load- and voltage-dependent: at VCC = 3.3 V and CL = 5 pF, tpd = 2.2 ns (typ); at VCC = 1.2 V and same load, tpd = 5.3 ns (typ). Power dissipation capacitance CPD is 2.8 pF (typ) at 1.2 V, enabling accurate dynamic power estimation using PD = CPD × VCC² × fi × N.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Single 2-input NAND gate with true Schmitt-trigger inputs for hysteresis-based noise rejection |
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains without level shifters |
| Max ICC (Static) | 0.9 μA at −40 °C to +125 °C - enables multi-year battery life in always-on sensor wake-up circuits |
| tpd (Typ) | 2.2 ns at VCC = 3.0 V, CL = 5 pF - sufficient for <50 MHz clock domain bridging in low-speed microcontroller peripherals |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents cross-conduction and bus contention during partial system power-down |
| ESD Rating | HBM >5000 V, CDM >1000 V - withstands handling in Class 0 ESD environments without external protection |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive body control modules and industrial motor drives |
Pinout & Package
TSSOP5 plastic thin shrink small outline package (SOT353-1), 5-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (B) | Data input | Non-inverting Schmitt-trigger input; accepts 0–3.6 V regardless of VCC, enabling mixed-voltage signal injection |
| 2 (A) | Data input | Non-inverting Schmitt-trigger input; electrically identical to Pin 1; supports dual-input logic gating |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output drivers; must be low-impedance for stable noise margin |
| 4 (Y) | Data output | Push-pull CMOS output; sinks/sourcing up to ±4 mA at 3.0 V; compatible with 5 V-tolerant inputs when VCC ≤ 3.3 V |
| 5 (VCC) | Supply voltage | Primary power rail; IOFF activation occurs automatically when voltage drops below ~0.2 V, disabling Y |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8–3.6 V operation eliminates need for separate LDOs in multi-rail systems like smart meters |
| Schmitt-trigger inputs | Input hysteresis ≥ 0.25×VCC ensures clean switching on slow edges from thermistors or potentiometers |
| IOFF partial power-down | Output high-impedance state activated at VCC = 0 V prevents backfeed into powered sections during hot-plug events |
| Low dynamic power | CPD = 2.8–4.2 pF enables sub-μW dynamic consumption at 1 MHz, critical for energy-harvesting designs |
| High noise immunity | VIL/VIH thresholds track VCC proportionally; noise margin exceeds 30% of VCC across full temperature range |
Applications
| Industrial Sensor Interface | Portable Medical Device Logic |
|---|---|
|
Use Scenario: Signal conditioning for analog switch debouncing and fault detection in PLC I/O modules. IC Role / Device Role / Timing Role: NAND gate configured as inverter with Schmitt input to clean noisy contact closure signals before MCU GPIO sampling. Use Value: Eliminates external RC filters and reduces BOM count by integrating hysteresis and logic in one 1.25 mm wide package. |
Use Scenario: Power sequencing control and button press validation in wearable ECG monitors. IC Role / Device Role / Timing Role: Enables/disables auxiliary sensors using NAND logic driven by low-power MCU pins; IOFF blocks leakage during sleep mode. Use Value: Extends coin-cell battery life beyond 2 years by limiting static current to ≤0.9 μA while maintaining fast wake-up response. |
| Automotive Body Control | IoT Edge Node Signal Routing |
|
Use Scenario: Interlock logic for door lock actuators and mirror position feedback in 12 V vehicle architectures. IC Role / Device Role / Timing Role: Combines two independent sensor inputs (e.g., latch closed + key fob proximity) to enable actuator driver only when both conditions met. Use Value: −40 °C to +125 °C rating and AEC-Q200-aligned construction ensure reliability in under-dash environments without derating. |
Use Scenario: Dynamic routing of UART/ADC signals between multiple MCUs in mesh-networked environmental sensors. IC Role / Device Role / Timing Role: Acts as enable gate for level-shifted communication lines; Schmitt inputs tolerate variable slew rates from different node transceivers. Use Value: 5-pin TSSOP footprint saves >40% board area vs. SOIC-8 alternatives while supporting 3.3 V ↔ 1.8 V domain bridging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G00DBVR | Wider VCC range (1.65–5.5 V); no Schmitt inputs; higher ICC (10 μA typ); no IOFF | Requires external hysteresis for noisy inputs; unsuitable for partial power-down systems | Select when interfacing with 5 V legacy peripherals and noise environment is controlled |
| 74LVC1G00GW,125 | Same TSSOP5 package; VCC = 1.65–5.5 V; VIH/VIL fixed thresholds (not VCC-proportional); no IOFF | Lacks Schmitt action and IOFF; higher propagation delay (3.5 ns min at 3.3 V); lower ESD rating (HBM 2000 V) | Choose only for cost-sensitive, non-battery, non-noisy applications where VCC ≥ 1.8 V is guaranteed |
Compared with SN74LVC1G00DBVR and 74LVC1G00GW,125, the 74AUP1G00GW,125 uniquely combines ultra-low ICC, Schmitt-trigger noise immunity, and IOFF-making it the sole option for long-life, mixed-voltage, hot-swap-capable logic in constrained embedded systems.
Availability
74AUP1G00GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control units, and IoT edge node signal routing requiring stable component supply across extended temperature ranges.
Supply support for 74AUP1G00GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in advanced packaging and automotive-grade qualification.
The 74AUP (Advanced Ultra Low Power) product line targets battery-operated and energy-constrained applications, emphasizing sub-1 μA static current, wide-VCC compatibility, and robust IOFF behavior for modern embedded systems.
FAQ
Does the 74AUP1G00GW,125 support true 0.8 V operation with full timing guarantees?
Yes. The datasheet specifies tpd ≤ 17.5 ns (typ) and VIH ≥ 0.70×VCC at VCC = 0.8 V, with ICC ≤ 0.5 μA (typ) and full functionality verified from −40 °C to +125 °C. All DC and AC parameters are characterized down to 0.8 V, making it suitable for direct connection to 0.8 V FPGA I/O banks.
Can Pin 5 (VCC) and Pin 3 (GND) be swapped during PCB layout?
No. Swapping VCC and GND will cause immediate device failure due to reverse biasing of internal ESD diodes and core logic transistors. The pinout is fixed per SOT353-1 mechanical drawing: Pin 1 = B, Pin 2 = A, Pin 3 = GND, Pin 4 = Y, Pin 5 = VCC. Misrouting violates absolute maximum ratings (VCC = −0.5 V min).
Is the Schmitt-trigger hysteresis adjustable or fixed?
Hysteresis is fixed and process-defined: typical ΔV = VIH − VIL ≈ 0.3×VCC at VCC = 1.2 V, increasing linearly with supply. No external components or configuration pins modify hysteresis-it is intrinsic to the input stage design and guaranteed across temperature and voltage.
What is the maximum capacitive load the 74AUP1G00GW,125 can drive while maintaining specified tpd?
The device is characterized up to CL = 30 pF, with tpd = 4.3 ns (typ) at VCC = 3.3 V. Driving >30 pF increases propagation delay nonlinearly and may degrade VOH/VOL margins; for loads >50 pF, a buffer stage or lower-impedance driver is recommended to maintain timing integrity.
74AUP1G00GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- NAND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.5ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74AUP1G00GW,125 FAQ
1.How can I place an order for 74AUP1G00GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1G00GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1G00GW,125 reliable?
The price and inventory of 74AUP1G00GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1G00GW,125 is usually 5 days.
3.What payment methods are accepted for 74AUP1G00GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1G00GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1G00GW,125?
74AUP1G00GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1G00GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1G00GW,125?
For technical support, including 74AUP1G00GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1G00GW,125 requirements.
6.How does Aetrix verify that 74AUP1G00GW,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1G00GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1G00GW,125 meets industry standards.
7.What is the process for return or replacement of 74AUP1G00GW,125?
All 74AUP1G00GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1G00GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1G00GW,125 part is unused and in its original packaging.
Return procedure for 74AUP1G00GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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