Nexperia USA Inc. 74AUP1G00GW-Q100H

Overview

74AUP1G00GW-Q100 from Nexperia is a single 2-input NAND gate with Schmitt-trigger inputs, rated for automotive Grade 1 (−40 °C to +125 °C), operating from 0.8 V to 3.6 V supply, featuring IOFF partial power-down protection and <0.9 μA max ICC at 25 °C.

For engineers reviewing the 74AUP1G00GW-Q100 datasheet, 74AUP1G00GW-Q100 pinout, 74AUP1G00GW-Q100 application, or 74AUP1G00GW-Q100 equivalent, this device serves as a low-power logic building block in battery-sensitive automotive subsystems, sensor interface conditioning, and voltage-level tolerant control signal routing where input noise immunity and power-down isolation are critical.

Technical Context

This device implements standard NAND logic with hysteresis on both inputs (Schmitt-trigger action), enabling robust operation with slow-rising or noisy signals without external filtering. Its IOFF circuit actively disables outputs when VCC = 0 V, preventing backflow current during partial system power-down.

It complies with multiple JEDEC voltage-tier standards (JESD8-12 through JESD8C) and supports dynamic operation across five VCC ranges (0.8–1.3 V, 1.4–1.6 V, etc.), with propagation delay as low as 1.0 ns (typ.) at 3.0–3.6 V and CL = 5 pF.

Key Specifications

Pinout & Package

TSSOP5 plastic thin shrink small outline package (SOT353-1), 5-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with 74LVC1G00GV-Q100 and SN74LVC1G00DPWR, the 74AUP1G00GW-Q100 uniquely combines Schmitt-trigger inputs, IOFF, ultra-low ICC (<0.9 μA), and AEC-Q100 Grade 1 - making it the sole choice for noise-prone, battery-sensitive, and safety-compliant automotive logic nodes.

Availability

74AUP1G00GW-Q100 is available at Aetrix Electronics and suitable for automotive body electronics, ADAS sensor interfaces, infotainment wake logic, and power sequencing requiring stable component supply across extended temperature and long product lifecycles.

Supply support for 74AUP1G00GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile applications.

The 74AUP (Advanced Ultra-low Power) series is designed specifically for energy-constrained automotive subsystems requiring sub-1 μA quiescent current, wide-VCC compatibility, and AEC-Q100 compliance without sacrificing speed or noise immunity.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G00GW-Q100 allows input voltages up to 3.6 V regardless of VCC state, as confirmed in Table 5 (VI input voltage: −0.5 V to +4.6 V) and Section 2 ("Overvoltage tolerant inputs to 3.6 V"). This enables hot-plug and mixed-voltage system interoperability even during full power-down.

Does this device support true bidirectional level shifting?

No - it is a unidirectional logic gate. While inputs tolerate up to 3.6 V at any VCC (including 0 V), the output swing is referenced to VCC and cannot drive loads referenced to a different rail. It performs level translation only in the input-to-output direction, not reverse.

How does the IOFF feature behave during VCC ramp-up or ramp-down?

IOFF activates when VCC falls below ~0.2 V and remains active until VCC exceeds ~0.5 V, as defined by ΔIOFF specification (±0.75 μA leakage when VCC = 0 V to 0.2 V). Output transitions to high-impedance before VCC reaches operational levels, preventing shoot-through during power sequencing.

Can this NAND gate drive a 50 pF load at 3.3 V while maintaining timing specs?

No - the datasheet specifies timing only up to CL = 30 pF (tpd ≤ 6.5 ns at 3.3 V). At 50 pF, propagation delay increases beyond guaranteed limits and output rise/fall times degrade. For >30 pF loads, a buffer stage or lower-capacitance layout is required to meet timing budgets.