Diodes Incorporated 74AUP1G00SE-7

Overview

74AUP1G00SE-7 from Diodes Incorporated is a single 2-input positive NAND gate in the Advanced Ultra Low Power (AUP) CMOS logic family, designed for battery-powered portable electronics. It operates across 0.8V–3.6V supply, delivers ±4 mA output drive at 3.0V, features IOFF partial power-down protection, and integrates Schmitt-trigger inputs with ~250 mV hysteresis at VCC = 3.0V - enabling robust signal conditioning in low-voltage sensor interface and power management circuits.

For engineers reviewing the 74AUP1G00SE-7 datasheet, 74AUP1G00SE-7 pinout, 74AUP1G00SE-7 application, or 74AUP1G00SE-7 equivalent, this device is selected for ultra-low static current (<0.9 µA), wide VCC tolerance, and guaranteed operation down to –40°C in space-constrained SOT353 packaging - critical for wearables, IoT edge nodes, and multi-rail power sequencing designs.

Technical Context

This NAND gate implements standard Boolean logic (Y = A·B) with push-pull CMOS outputs and Schmitt-trigger inputs that tolerate slow-rising signals and suppress noise on noisy PCB traces. Its IOFF circuit actively disables output leakage during partial power-down, preventing backflow current when VCC is off while other system rails remain active.

The device supports full rail-to-rail input voltage range (0 to VCC) and guarantees propagation delay as low as 1.0 ns (typ.) at 3.3V with 5 pF load. Input thresholds scale with VCC (e.g., VIH = 0.8×VCC at 0.8–1.65V), ensuring reliable logic interpretation across its entire operating voltage window.

Key Specifications

Pinout & Package

SOT353 (2.0 mm × 2.0 mm × 1.1 mm, 0.65 mm lead pitch) - a 5-pin leaded package optimized for reflow compatibility and optical inspection in high-volume portable manufacturing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NAND gate applications.

Compared with SN74LVC1G00DBVR and 74AHC1G00SE-7, the 74AUP1G00SE-7 uniquely balances ultra-low ICC, wide VCC scalability, Schmitt-trigger noise rejection, and IOFF - making it the only option among the three qualified for true multi-rail, battery-sensitive, and EMI-prone portable applications.

Availability

74AUP1G00SE-7 is available at Aetrix Electronics and suitable for wearable health monitors, IoT edge sensor hubs, and USB-C power delivery sequencers requiring stable component supply across extended product lifecycles and global manufacturing sites.

Supply support for 74AUP1G00SE-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and logic solutions for power management, signal integrity, and connectivity applications - with design centers in Asia, Europe, and North America.

The 74AUP logic family targets ultra-low-power portable electronics, delivering industry-leading static current and wide-voltage interoperability for battery-constrained devices such as wearables, medical sensors, and wireless edge nodes.

FAQ

What is the minimum supply voltage for guaranteed operation?

The 74AUP1G00SE-7 is fully specified from 0.8V to 3.6V. At 0.8V, propagation delay is 17.5 ns (typ.) with 5 pF load, and input thresholds scale to 0.8×VCC. Operation below 0.8V is not characterized and may result in undefined logic states or increased ICC.

Can unused inputs be left floating?

No. Per datasheet Note 8, unused inputs must be tied to VCC or GND to prevent increased ICC, oscillation, or latch-up. Floating inputs cause unpredictable current draw and potential logic instability due to CMOS input structure sensitivity.

Does the SOT353 package support automated optical inspection (AOI)?

Yes. The SOT353 package has exposed leads and standardized 0.65 mm pitch, enabling reliable AOI in high-volume SMT lines. Diodes' AP02002 pad layout document specifies solder mask and stencil recommendations to ensure consistent reflow yield and void-free joints.

How does IOFF behave during partial power-down?

When VCC = 0V, the IOFF circuit disables both input and output paths, limiting leakage current to ≤0.6 µA (max) even if A, B, or Y are biased to 3.6V. This prevents back-current flow into a powered-down section - critical for hot-swap interfaces and multi-rail power sequencing.