Nexperia USA Inc. 74AUP1G02GM,132

Overview

74AUP1G02GM,132 from Nexperia is a single 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 0.8 ns at 3.6 V with 5 pF load - deployed in battery-powered sensor interfaces and low-voltage microcontroller I/O expansion.

For engineers reviewing the 74AUP1G02GM,132 datasheet, 74AUP1G02GM,132 pinout, 74AUP1G02GM,132 application, or 74AUP1G02GM,132 equivalent, key selection criteria include its 6-terminal XSON6 (SOT886) package, guaranteed operation up to +125 °C, sub-1 V logic compatibility, and IOFF leakage < ±0.75 μA during power-down - critical for always-on subsystems and energy-harvesting nodes.

Technical Context

This device implements standard positive-logic NOR functionality (Y = NOT(A OR B)) with hysteresis on both inputs, enabling robust noise immunity against slow-rising signals and rail-to-rail input tolerance up to 3.6 V regardless of VCC. Its CMOS architecture ensures rail-aligned output swing and near-zero static power draw.

The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current between powered and unpowered domains - a requirement for hot-swap I/O buffering and multi-rail system partitioning. Input transition rate support up to 200 ns/V further accommodates legacy or RC-filtered signal sources.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flanks not present; thermal pad absent.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NOR gate applications.

Compared with 74LVC1G02GW,125 and SN74AUP1G02DBVR, the 74AUP1G02GM,132 uniquely combines Schmitt-trigger inputs, 0.8 V operation, and IOFF in a 1.0 × 1.45 mm XSON6 package - making it optimal for space-constrained, ultra-low-power, multi-rail embedded designs requiring noise-hardened logic.

Availability

74AUP1G02GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, wearable health monitors, and smart home edge nodes requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP1G02GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions - serving automotive, industrial, and consumer markets with AEC-Q100-qualified components and scalable manufacturing.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-operated and energy-sensitive applications, emphasizing sub-1 V operation, nanowatt static power, and robust IOFF behavior for modern mixed-supply architectures.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G02GM,132 supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC state. When VCC = 0 V, inputs may safely remain at up to 3.6 V without damage or excessive leakage - a key enabler for hot-swap and multi-rail isolation use cases.

Does the n.c. pin require PCB routing or thermal relief?

No. Pin 4 is internally unconnected and must remain electrically floating. It does not require a PCB trace, solder mask opening, or thermal pad. Leaving it unconnected avoids unintended coupling or parasitic capacitance that could affect timing margins.

How does IOFF behavior differ from standard CMOS high-impedance mode?

IOFF actively disables the output buffer when VCC = 0 V, clamping leakage to ≤ ±0.75 μA. Unlike tri-state outputs, which require active control signals, IOFF is automatic and voltage-triggered - eliminating risk of bus contention during power sequencing or partial shutdown.

Can this device drive a 50 pF load reliably?

No. The datasheet specifies dynamic performance only up to 30 pF load capacitance. At 50 pF, propagation delay increases beyond guaranteed limits (e.g., >8.5 ns at 3.6 V), and output rise/fall times degrade. For >30 pF loads, add a buffer stage or reduce trace length and stubs.