Nexperia USA Inc. 74AUP1G02GN,132

Overview

74AUP1G02GN,132 from Nexperia is a single 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 0.8 ns at 3.6 V/5 pF. It serves as a noise-immune signal combiner in battery-powered sensor interfaces and level-shifting control paths.

For engineers reviewing the 74AUP1G02GN,132 datasheet, 74AUP1G02GN,132 pinout, 74AUP1G02GN,132 application, or 74AUP1G02GN,132 equivalent, key selection criteria include its 0.8–3.6 V wide-VCC operation, IOFF leakage < ±0.75 μA during power-down, Schmitt-trigger input hysteresis for slow-edge tolerance, and XSON6 (SOT1115) 0.9 × 1.0 × 0.35 mm package compatibility with high-density PCB layouts.

Technical Context

This device implements standard positive-logic NOR functionality (Y = NOT(A OR B)) with integrated Schmitt-trigger inputs-providing ≥0.3×VCC hysteresis-to reject noise on slow-rising/falling signals in mixed-voltage systems. Its IOFF circuit actively disables output terminals when VCC = 0 V, blocking backflow current up to ±0.75 μA.

Designed for ultra-low-power operation, it achieves dynamic power dissipation via CPD = 4.1 pF (at 3.6 V) and supports load capacitances up to 30 pF while maintaining tpd ≤ 4.4 ns over −40 °C to +125 °C at VCC = 3.0–3.6 V and CL = 5 pF.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount device with 0.9 mm × 1.0 mm × 0.35 mm body dimensions and wettable flank-compatible footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NOR gate applications.

Compared with 74LVC1G02GW,125, the 74AUP1G02GN,132 delivers 90% lower static current and essential IOFF protection; versus SN74AUP1G02DBVR, it offers superior thermal derating (3.2 mW/K vs. 3.0 mW/K) and enhanced manufacturability via side-wettable flanks in SOT1115.

Availability

74AUP1G02GN,132 is available at Aetrix Electronics and suitable for industrial sensor nodes, wearable health monitors, automotive body controllers, and USB-C power arbitration circuits requiring stable component supply across extended temperature ranges.

Supply support for 74AUP1G02GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications demanding sub-microwatt static operation, robust noise immunity, and seamless voltage-domain interoperability - exemplified by the 74AUP1G02GN,132's 0.8–3.6 V range and IOFF architecture.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP1G02GN,132 permits input voltages up to 3.6 V even with VCC = 0 V, thanks to overvoltage-tolerant input structures. This allows safe signal injection during power-down sequences without risk of latch-up or damage, provided input current remains within ±50 mA per IEC 60134 limiting values.

Does the Schmitt-trigger input affect propagation delay specifications?

Yes - Schmitt-trigger action adds minimal delay (<0.2 ns typical) versus non-hysteresis inputs but enables consistent timing across varying slew rates. Propagation delay values in Table 8 and Table 9 are measured with standard test waveforms (tr/tf ≤ 200 ns/V) and include Schmitt-trigger contribution; no derating is needed for slow edges.

Can pin 5 (n.c.) be grounded or tied to VCC for mechanical stability?

No - pin 5 is internally unconnected and must remain floating. Connecting it to GND, VCC, or any other node violates the SOT1115 design and may cause unpredictable behavior or increased leakage. Mechanical stability is ensured by soldering only pins 1–4 and 6 per the recommended footprint in Figure 8.

How does IOFF behave during VCC ramp-up from 0 V to nominal voltage?

IOFF remains active until VCC exceeds ~0.2 V, at which point output drivers gradually enable. During this transition (0 V < VCC < 0.2 V), ΔIOFF leakage is specified ≤ ±0.75 μA - ensuring no disruptive current injection into downstream circuits while preserving safe power sequencing in multi-rail systems.