Nexperia USA Inc. 74AUP1G02GW,125

Overview

74AUP1G02GW,125 from Nexperia is a single 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering 0.9 μA max ICC at 25 °C, -40 °C to +125 °C temperature range, and 3.4 ns max propagation delay at 3.6 V/5 pF - used in low-power level-shifting and noise-immune signal conditioning in portable sensor interfaces.

For engineers reviewing the 74AUP1G02GW,125 datasheet, 74AUP1G02GW,125 pinout, 74AUP1G02GW,125 application, or 74AUP1G02GW,125 equivalent, key selection criteria include IOFF-enabled partial power-down capability, overvoltage-tolerant 3.6 V inputs at sub-1 V VCC, and guaranteed operation down to 0.8 V for ultra-low-voltage microcontroller I/O interfacing.

Technical Context

This device implements standard CMOS NOR logic with hysteresis on both inputs (Schmitt-trigger), enabling robust operation with slow-rising signals and high noise immunity in mixed-voltage systems. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current in partial power-down modes.

It complies with JEDEC standards JESD8-12 through JESD8-B across five VCC ranges and meets ANSI/ESDA/JEDEC JS-001 Class 3A (5000 V HBM) and JS-002 Class C3 (1000 V CDM) ESD requirements - confirming suitability for handheld and industrial edge-node PCBs with unshielded I/O traces.

Key Specifications

Pinout & Package

TSSOP5 plastic thin shrink small outline package (SOT353-1), 5-lead, 1.25 mm body width, 0.65 mm pitch, exposed pad not present - optimized for automated optical inspection and reflow compatibility in high-density PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NOR gate applications.

Compared with SN74LVC1G02DBVR and 74LVC1G02GW,125, the 74AUP1G02GW,125 uniquely delivers sub-1 V operation, Schmitt-trigger noise rejection, and IOFF-enabled safe power sequencing - making it the only option for energy-harvesting and automotive domain-controller I/O consolidation.

Availability

74AUP1G02GW,125 is available at Aetrix Electronics and suitable for portable medical devices, automotive body control units, industrial PLC input cards, and consumer smart home hubs requiring stable component supply across extended temperature and ultra-low-power constraints.

Supply support for 74AUP1G02GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions - spun off from NXP in 2017 and headquartered in Nijmegen, Netherlands.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and thermally constrained applications where sub-1 μA static current, wide VCC scalability, and robust ESD performance are mandatory design requirements.

FAQ

Does 74AUP1G02GW,125 support true bidirectional I/O?

No. It is a unidirectional NOR gate with dedicated inputs (A, B) and output (Y). The IOFF feature only places Y in high-impedance during VCC = 0 V - it does not enable bus-sharing or data direction control. Bidirectional operation requires external control logic or a dedicated transceiver IC.

Can 74AUP1G02GW,125 drive a 50 pF load reliably?

Yes, but with increased propagation delay: typical tpd rises to ~6.4 ns at VCC = 3.6 V and CL = 30 pF (max rated), and extrapolates to ~8.5 ns at 50 pF. For timing-critical paths, limit load to ≤15 pF or add series termination to manage ringing without degrading noise margin.

What is the maximum allowable input voltage when VCC = 0 V?

Inputs tolerate up to 3.6 V independent of VCC per datasheet Table 5 (VI input voltage: -0.5 V to +4.6 V). This overvoltage capability enables safe "live insertion" of boards and hot-swap I/O expansion - confirmed by 5000 V HBM and 1000 V CDM ESD ratings.

Is the GND pin (Pin 3) internally bonded to the die substrate?

Yes. In the SOT353-1 (TSSOP5) package, Pin 3 is the sole GND terminal and serves as the primary thermal and electrical reference for the silicon die. No internal substrate tie exists outside this pin - proper PCB grounding with ≥2 vias directly beneath the package is required to meet thermal derating curves and maintain <10 % VCC noise.