Nexperia USA Inc. 74AUP1G02GW-Q100H

Overview

74AUP1G02GW-Q100 from Nexperia is a single 2-input automotive-grade NOR gate with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering <0.9 μA max ICC at 125 °C, IOFF-enabled partial power-down protection, and AEC-Q100 Grade 1 qualification for under-hood control logic in body electronics and ADAS sensor interfaces.

For engineers reviewing the 74AUP1G02GW-Q100 datasheet, 74AUP1G02GW-Q100 pinout, 74AUP1G02GW-Q100 application, or 74AUP1G02GW-Q100 equivalent, this device supports low-voltage logic interfacing in battery-supplied automotive modules, offers robust noise immunity via Schmitt-trigger inputs, and enables safe I/O isolation during system sleep states using its IOFF circuitry.

Technical Context

This device implements a single 2-input NOR function with true Schmitt-trigger input thresholds-VIH ≥ 0.65×VCC and VIL ≤ 0.35×VCC across 0.9–1.95 V VCC-to tolerate slow-rising signals from sensors or mechanical switches. Its IOFF circuit actively disables output leakage when VCC = 0 V, limiting backflow current to ±0.75 μA over –40 °C to +125 °C.

Propagation delay is load- and voltage-dependent: tpd = 1.0–3.4 ns (CL = 5 pF, VCC = 3.0–3.6 V) and up to 8.5 ns (CL = 30 pF, VCC = 3.0–3.6 V, –40 °C to +125 °C). Input capacitance is 0.8 pF; output capacitance is 1.7 pF-enabling high-speed, low-power signal conditioning in space-constrained PCB layouts.

Key Specifications

Pinout & Package

TSSOP5 plastic thin shrink small outline package (SOT353-1), 5-lead, 1.25 mm body width, 0.65 mm lead pitch, designed for reflow-compatible surface-mount assembly in automotive PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NOR gate applications.

Compared with 74LVC1G02GV-Q100 and SN74LVC1G02DPWRQ1, the 74AUP1G02GW-Q100 delivers the lowest static power (0.9 μA), smallest TSSOP5 footprint, and guaranteed IOFF behavior-making it optimal for space- and energy-sensitive automotive control nodes where partial power-down integrity is mandatory.

Availability

74AUP1G02GW-Q100 is available at Aetrix Electronics and suitable for automotive body electronics, ADAS sensor fusion, power distribution units, and infotainment wake-up logic requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1G02GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer headquartered in Nijmegen, Netherlands, specializing in high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP1G02-Q100 belongs to Nexperia's Automotive Ultra Low-Power (AUP) logic family-designed specifically for energy-efficient, AEC-Q100-qualified signal conditioning in next-generation vehicle electronic control units.

FAQ

What is the maximum propagation delay at 125 °C and 3.3 V VCC with 30 pF load?

At Tamb = +125 °C, VCC = 3.3 V, and CL = 30 pF, the maximum propagation delay (tpd) is 8.5 ns, as specified in Table 9 of the datasheet. This value accounts for worst-case process, voltage, and temperature (PVT) corners and ensures timing compliance in high-temperature automotive environments such as engine control modules.

Can 74AUP1G02GW-Q100 safely interface with 5 V logic signals?

No. While inputs are overvoltage tolerant to 3.6 V, applying 5 V violates the absolute maximum input voltage rating (VI = –0.5 V to +4.6 V only when clamping current limits are observed). Sustained 5 V input risks exceeding IIK = –50 mA clamp current and may cause permanent damage. Level-shifting is required for 5 V system integration.

How does the IOFF feature behave when VCC is ramping down during system shutdown?

IOFF activates when VCC falls below approximately 0.2 V, disabling the output stage and limiting leakage to ±0.75 μA. This prevents reverse current flow from powered I/O lines (e.g., 3.3 V CAN transceiver) into the unpowered gate, protecting both devices and maintaining signal integrity during controlled power sequencing.

Is the Schmitt-trigger hysteresis adjustable or fixed?

The Schmitt-trigger hysteresis is fixed and process-defined: VIH – VIL ≈ 0.3×VCC minimum across 0.9–1.95 V VCC. It is not user-adjustable. The hysteresis width increases with VCC, providing consistent noise margin scaling-e.g., ~300 mV at 1.0 V and ~1.1 V at 3.6 V-without external components.