STMicroelectronics 74AUP1G04DTR

Overview

74AUP1G04DTR from STMicroelectronics is a low-power CMOS single inverter gate operating from 1.2 V to 3.6 V, delivering 4.3 ns max propagation delay at 2.3 V, 1 µA max quiescent current at 85 °C, and ESD immunity up to 2000 V HBM. It serves as a level-shifting signal inverter in battery-powered portable logic interfaces.

For engineers reviewing the 74AUP1G04DTR datasheet, 74AUP1G04DTR pinout, 74AUP1G04DTR application, or 74AUP1G04DTR equivalent, key selection criteria include supply voltage flexibility (1.2–3.6 V), ultra-low ICC, balanced tPLH/tPHL timing, and DFN6L package compatibility with high-density PCB layouts.

Technical Context

This device implements a single unbuffered inverting logic function using sub-micron C2MOS technology, supporting rail-to-rail input/output swing and power-down protection on all pins. Its input threshold scales with VCC (VIH = 0.65×VCC at 1.2–1.95 V), enabling robust operation across multiple supply domains.

The output stage drives ±4 mA minimum at 1.2 V and ±10 mA at 3.0 V while maintaining VOL ≤ 0.25 V and VOH ≥ VCC – 0.2 V. Input capacitance is 3 pF, and power dissipation capacitance is 32 pF at 10 MHz - optimized for low-noise, low-energy switching in portable systems.

Key Specifications

Pinout & Package

74AUP1G04DTR uses the DFN6L (1.2 × 1.0 mm) leadless package with wettable flanks, compatible with automated optical inspection (AOI) and reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverter gate applications.

Compared with Nexperia 74AUP1G04GW and TI SN74LVC1G04DBVR, the 74AUP1G04DTR uniquely supports 1.2 V operation with lowest ICC and DFN6L's space efficiency - critical for compact, multi-rail portable designs.

Availability

74AUP1G04DTR is available at Aetrix Electronics and suitable for mobile phone baseband interfaces, wearable sensor signal conditioning, Bluetooth LE module reset control, and smartwatch display backlight enable logic requiring stable component supply and long-term lifecycle assurance.

Supply support for 74AUP1G04DTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and sensors for industrial, automotive, and consumer markets.

The 74AUP logic family targets ultra-low-power portable electronics, emphasizing sub-2 V operation, nanowatt static consumption, and miniature packaging - directly addressing design constraints in wearables and IoT edge nodes.

FAQ

Is 74AUP1G04DTR pin-compatible with other AUP-series inverters in DFN6L?

Yes - all 74AUP1Gxx devices in DFN6L (e.g., 74AUP1G00, 74AUP1G02, 74AUP1G04, 74AUP1G08) share identical pinout: Pin 2 = input, Pin 4 = output, Pin 3 = GND, Pin 6 = VCC, Pins 1/5 = NC. This allows footprint reuse across logic functions in space-constrained designs.

Can 74AUP1G04DTR safely interface between 1.2 V and 3.3 V domains?

Yes - its inputs tolerate voltages up to VCC + 0.5 V (absolute max 4.6 V), and outputs swing rail-to-rail. When VCC = 3.3 V, it accepts 1.2 V logic-high as valid (VIH min = 2.0 V), but a level shifter is required for reliable 1.2 V → 3.3 V translation; the device itself does not translate levels.

What is the maximum capacitive load this inverter can drive reliably?

At VCC = 3.3 V, it drives 15 pF loads with tPD ≤ 2.9 ns (–40 to 85 °C). For 30 pF, tPD rises to ≤ 3.8 ns - still functional, but timing margins shrink. For loads >30 pF, add series termination or buffer stages to maintain signal integrity and avoid ringing.

Does 74AUP1G04DTR require external pull-up or pull-down resistors on unused pins?

No - Pins 1 and 5 are internally unconnected (NC) with no bond wire. They may be left floating, tied to GND, or used for thermal relief. No current path exists, so no resistor is needed. However, grounding them improves mechanical reliability during reflow.